Sample rate conversion filter design for multi-standard software radios

Sheikh, F.; Masud, Shahid

doi:10.1016/j.dsp.2009.04.014

Cited by 17 publications

(14 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The two approaches presented above require an explicit fractional SRC filter to meet the data rate requirements of the radio standard. A joint compensation and interpolation filter based on frequency domain polynomials for multi-standard radio receivers is proposed in literature [30]. The filter designed using this approach has a unified architecture for the all the three filters and shown in Fig.…”

Section: Joint Compensation and Interpolation Methodsmentioning

confidence: 99%

“…In contrast to the above methods, the proposed designed method offers high degree of flexibility to adapt to any existing or The hardware complexities of DDC-SRC employing various methods are summarised in Table 3. It may be observed from the Table 3 that the proposed method and Sheikh's method [30] requires less number of MAC units compared with the FRMFB and conventional method [18], as these methods do not require explicit CFIR and fractional rate SRC filters. It may be noted that the proposed architecture require slightly more hardware by LP number of MAC units compared with Sheikh's method [30].…”

Section: Hardware Complexitymentioning

confidence: 99%

“…It may be observed from the Table 3 that the proposed method and Sheikh's method [30] requires less number of MAC units compared with the FRMFB and conventional method [18], as these methods do not require explicit CFIR and fractional rate SRC filters. It may be noted that the proposed architecture require slightly more hardware by LP number of MAC units compared with Sheikh's method [30]. However, proposed architecture offers tunability for supporting multistandard radio communications in contrast to the other architectures considered for comparison in Table 3.…”

Section: Hardware Complexitymentioning

confidence: 99%

See 2 more Smart Citations

SVD based reconfigurable SRC filter for multi‐standard radio receivers

Agarwal

Bopanna

2016

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

With the recent growth in wireless industry, and changes that occur at a faster pace in radio standards, software defined radio (SDR) provides a flexible solution when compared with hardware radios. Channelisation and sample rate conversion (SRC) are two computational intensive tasks to be carried out in SDR receivers. Reconfigurable anti-aliasing filter and channeliser with minimum reconfiguration overhead is needed for the design of SDR receivers. Low complexity, coefficientless cascaded-integrator-comb filters provides flexible reconfiguration for SRC over a wide integer range, but offers gain droop in the passband of interest. Moreover, they are not suitable for achieving SRC by fractional rates. In this study, the authors propose the design of variable digital filter (VDF) for gain droop compensation and fractional SRC to meet the spectral characteristics of multiple radio communication standards, employing singular value decomposition algorithm. The proposed design of VDF is tested for its reconfigurability with four radio standards, namely, GSM900, WCDMA/CDMA 2000 and WiMAX 802.16. Simulations carried out in MATLAB showed that the proposed VDF had improved spectral response in comparison to other methods proposed in literature.

show abstract

Section: Joint Compensation and Interpolation Methodsmentioning

confidence: 99%

Section: Hardware Complexitymentioning

confidence: 99%

Section: Hardware Complexitymentioning

confidence: 99%

See 1 more Smart Citation

SVD based reconfigurable SRC filter for multi‐standard radio receivers

Agarwal

Bopanna

2016

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…Compared to the other blocks on the baseband processing platform, the SRC is the most DSP heavy block that requires around 50 % of the available DSP48E slices. [12] has shown, that a solution based on polynomial interpolation in combination with CIC filters is the most efficient one in terms of performance. [12] has shown, that a solution based on polynomial interpolation in combination with CIC filters is the most efficient one in terms of performance.…”

Section: Comparison Of Existing Solutionsmentioning

confidence: 99%

Hardware Optimized Sample Rate Conversion for Software Defined Radio

Schmidt-Knorreck¹,

Knopp²,

Pacalet³

2010

Frequenz

View full text Add to dashboard Cite

The evolution towards applications with increasing functionalities leads to the need of high flexible systems that support a high number of different standards while decreasing the required hardware space. Therefore a high configurable platform being able to handle a multitude of standards is needed. One main issue is the tradeoff between performance and space consumption. We present a generic, flexible, fractional and hardware optimized SRC architecture in the context of SDR, providing one architecture to process up to 8 different complex channels. The solution is based on bandlimited interpolation and allows processing by supporting a 1Hz resolution of the sampling rates.

show abstract

“…A challenging component in software defined radio (SDR) design is the digital IF section, which provides the flexibility of processing multiple channels of different standards [7]. Sample rate conversion (decimation and interpolation) is an important requirement of digital IF section as SDR has to run on a single clock where it has to support multiple standards with different data rate.…”

Section: Introductionmentioning

confidence: 99%

Low power and low complexity implementation of LPTV interpolation filter

Sridevi

Dhuli

Baboji

2016

2016 International Conference on Computer Communication and Informatics (ICCCI)

View full text Add to dashboard Cite

This paper presents an architecture for low power and low complexity implementation of a linear periodically time varying (LPTV) interpolation filter using thread decomposition (TD) technique which decomposes a filter into finite computational threads. TD technique enables us to develop the proposed architecture as a generalization to linear time invariant (LTI) filter structure. The area complexity of the proposed architecture is significantly reduced by optimizing the concurrent threads of the conventional design. Reduction of power consumption is achieved in the proposed design by eliminating futile multiplications and reducing the operating frequency of the multipliers. It involves nearly one fourth the number of adders, multipliers and delay elements compared to the conventional design. The proposed structure is implemented on Virtex FPGA 2vp30-7ff896. From the synthesis results, it is found that the proposed design offers 35.7% reduction in power consumption and 20.6% reduction in device utilization over the conventional design.

show abstract

Sample rate conversion filter design for multi-standard software radios

Cited by 17 publications

References 23 publications

SVD based reconfigurable SRC filter for multi‐standard radio receivers

SVD based reconfigurable SRC filter for multi‐standard radio receivers

Hardware Optimized Sample Rate Conversion for Software Defined Radio

Low power and low complexity implementation of LPTV interpolation filter

Contact Info

Product

Resources

About