Sampled simulation of multi-threaded applications

Abstract

Abstract-Sampling is a well-known workload reduction technique that allows one to speed up architectural simulation while accurately predicting performance. Previous sampling methods have been shown to accurately predict single-threaded application runtime based on its overall IPC. However, these previous approaches are unsuitable for general multi-threaded applications, for which IPC is not a good proxy for runtime. Additionally, we find that issues such as application periodicity and inter-thread synchronization play a significant role in determining how best to sample these applications.The proposed multi-threaded application sampling methodology is able to derive an effective sampling strategy for candidate applications using architecture-independent metrics. Using this methodology, large input sets can now be simulated which would otherwise be infeasible, allowing for more accurate conclusions to be made than from studies using scaled-down input sets. Through the use of the proposed methodology, we can simulate less than 10% of the total application runtime in detail. On the SPEComp, NPB and PARSEC benchmarks, running on an 8-core simulated system, we achieve an average absolute error of 3.5%.

Accurate off-line phase classification for HW/SW co-designed processors

“…However, the traditional phase classification is based on the clustering using the Basic Block Vector (BBV). Recent studies show that BBV does not behave well in the presence of frequent L2 misses [3,7]. What differentiates our work from the previous contributions is that we perform phase classification analysis for HW/SW co-designed architectures, where the effects of the dynamically execution and the staged compilation cause different application behavior.…”

“…However, for the cases with a significant number of nondeterministic long latency events (like for example L2 misses) CP I bb varies widely across executions [3,7]. Consequently, BBV phase classification in this case will give inaccurate results.…”

Current challenges in simulations of HPC systems

“…In addition, application synchronization timing effects must be taken into account during fast forwarding phases between sampling periods. Otherwise, the accuracy of execution time estimates provided by sampling decreases [17].…”

An Evaluation of High-Level Mechanistic Core Models

“…Several solutions have been proposed to address this issue, including workload sampling [Sherwood et al 2002;Wunderlich et al 2003;Ardestani and Renau 2013;Carlson et al 2013Carlson et al , 2014, and simulation acceleration through software optimization [Sanchez and Kozyrakis 2013] and FPGA hardware [Krasnov et al 2007;Chiou et al 2007;Chung et al 2008;Pellauer et al 2011]. …”