Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability

Zhang, Grace Li; Li, Bing; Schlichtmann, Ulf

doi:10.3850/9783981537079_0250

Cited by 14 publications

(8 citation statements)

References 7 publications

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“…From this comparison, we can see that our method produces a better yield, because we have the correlation information from emulated samples. The method proposed in [1] uses the same concept in this paper, but it captures the locations of buffers by processing emulated samples once at a time. Therefore, the relation between tuning values in different samples is not incorporated.…”

Section: Resultsmentioning

confidence: 99%

“…Therefore, the relation between tuning values in different samples is not incorporated. In addition, the method in [1] uses a purely random sequence so that the number of samples is still large. To verify the improvement of the proposed method, we mapped the circuits used in [1] to the same library and tested the yield improvement with respect to µ T .…”

Section: Resultsmentioning

confidence: 99%

“…A preliminary version of this paper was published as [1] in the Proceedings of the Design, Automation and Test in Europe (DATE) conference, 2016. The major improvement of this paper over [1] is to process multiple samples with an iterative learning procedure using a low-discrepancy sample sequence (Sobol sequence).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

Zhang

Liu

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-At submicron manufacturing technology nodes, process variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin to maintain yield, leading to an unaffordable overdesign. Most of these margins, however, are wasted after manufacturing, because process variations cause only some chips to be really slow, while other chips can easily meet given timing specifications. To reduce this pessimism, we can reserve less timing margin and tune failed chips after manufacturing with clock buffers to make them meet timing specifications. With this post-silicon clock tuning, critical paths can be balanced with neighboring paths in each chip specifically to counter the effect of process variations. Consequently, chips with timing failures can be rescued and the yield can thus be improved. This is specially useful in highperformance designs, e.g., high-end CPUs, where clock binning makes chips with higher performance much more profitable. In this paper, we propose a method to determine where to insert post-silicon tuning buffers during the design phase to improve the overall profit with clock binning. This method learns the buffer locations with a Sobol sequence iteratively and reduces the buffer ranges afterwards with tuning concentration and buffer grouping. Experimental results demonstrate that the proposed method can achieve a profit improvement of about 14% on average and up to 26%, with only a small number of tuning buffers inserted into the circuit.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

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Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

Zhang

Liu

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Furthermore, the methods in Refs. [81], [82] solves this problem with a sampling-based method to recognize a limited number of locations to insert tunable buffers for yield improvement, while the computational complexity of this method is reduced using machine learning in Ref. [83].…”

Section: Post-silicon Clock Tuningmentioning

confidence: 99%

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

Bing

Hashimoto

Schlichtmann

2018

IPSJ Transactions on System LSI Design Methodology

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In advanced technology nodes, transistors and interconnects with shrinking physical dimensions suffer large process variations during manufacturing and are prone to reliability issues. These underlying changes require an overhaul of the design methodologies for digital circuits. In this paper, we provide an overview of techniques introduced recently to analyze the effect of uncertainty in manufacturing and reliability issues of devices due to the diminishing feature size. These techniques range from variation/aging modeling to circuit-level analysis. In addition, active techniques to counter these effects, such as clock skew tuning and voltage tuning are also covered in this paper.

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“…Considering variation, various techniques are proposed, such as post-silicon tuning techniques [21,22], but they are the tuning techniques that cannot be used as the analysis in advance. SPICE Monte Carlo (MC) is considered an accurate method for variation analysis, however, it needs extremely large computational effort and is impractical for large designs.…”

Section: Introductionmentioning

confidence: 99%

Novel Prediction Framework for Path Delay Variation Based on Learning Method

et al. 2020

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Path delay variation becomes a serious concern in advanced technology, especially for multi-corner conditions. Plenty of timing analysis methods have been proposed to solve the issue of path delay variation, but they mainly focus on every single corner and are based on a characterized timing library, which neglects the correlation among multiple corners, resulting in a high characterization effort for all required corners. Here, a novel prediction framework is proposed for path delay variation by employing a learning-based method using back propagation (BP) regression. It can be used to solve the issue of path delay variation prediction under a single corner. Moreover, for multi-corner conditions, the proposed framework can be further expanded to predict corners that are not included in the training set. Experimental results show that the proposed model outperforms the traditional Advanced On-Chip Variation (AOCV) method with 1.4X improvement for the prediction of path delay variation for single corners. Additionally, while predicting new corners, the maximum error is 4.59%, which is less than current state-of-the-art works.

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Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability

Cited by 14 publications

References 7 publications

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

Novel Prediction Framework for Path Delay Variation Based on Learning Method

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