SAR TDC Architecture with Self-Calibration Employing Trigger Circuit

Ozawa, Yuki; Ida, Takashi; Jiang, Richen; Sakurai, Shotaro; Takigami, Seiya; Tsukiji, Nobukazu; Shiota, Ryoji; Kobayashi, Haruo

doi:10.1109/ats.2017.29

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…The SAR TDC, like the SAR ADC, uses only a single time comparator, unlike the flash and vernier architectures. However, the drawback of using the SAR TDC is that the original delay signals T STR and T STP need to be regenerated using a ring oscillator which consumes a lot of power and adds uncertainty due to the jitter from the ring oscillator [26,27].…”

Section: Flash Tdcmentioning

confidence: 99%

Successive Approximation Analog-to-Digital Converters In Time-Mode Signal Processing

Siddiqui

2024

Preprint

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<p>The need for Time-Mode Signal processing is discussed. A background for Analog-To-Digital Converters is reviewed. Different approaches and key building blocks of Time Mode Analog-to-Digital conversion are discussed. A new approach for Successive Approximation Register (SAR) Time-to-Digital Converter (TDC) which is called Double Edge SAR TDC is presente. A 4-bit implementation of the Double Edge SAR TDC is done in 65nm TSMC technology and compared against a standard implementation. The new 4-bit design is the Double Edge SAR TDC is able to achieve an ENOB of 3.91 bits and is able to achieve 24% power saving over the classic architecture. The Double Edge SAR TDC is then integrated in a 7-bit two-step Time Domain ADC which was able to achieve an ENOB of 5.312 bits and FOM of 173.5 fJ/conv.</p>

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Section: Flash Tdcmentioning

confidence: 99%

Successive Approximation Analog-to-Digital Converters In Time-Mode Signal Processing

Siddiqui

2024

Preprint

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“…Using the trigger circuits, the rising-edge timing difference between two input timing signals can be held. This enables the SAR TDC to measure the timing when two timing inputs are single-shot as well as repetitive two clocks [73].…”

Section: Sar Tdc With Trigger Circuitmentioning

confidence: 99%

How the Author's Group Came Up with Ideas in Analog/Mixed-Signal Circuit and System Area

KOBAYASHI

2024

IEICE Trans. Fundamentals

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This article reviews the author's group research achievements in analog/mixed-signal circuit and system area with introduction of how they came up with the ideas. Analog/mixed-signal circuits and systems have to be designed as well-balanced in many aspects, and coming up ideas needs some experiences and discussions with researchers. It is also heavily dependent on researchers. Here, the author's group own experiences are presented as well as their research motivations.

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“…TDC architectures range from the traditional Tapped Delay Line (TDL) [18] to Vernier interpolation methods [19]. Furthermore, successive approximation methods [28,29] are also very popular in analog-to-digital converters (ADCs); multi-edge TDCs [23] have been employed to further improve their performance, whereas innovative methods such as wave union TDCs [21] aim to improve resolution at the expense of complex encoding schemes and larger area requirements.…”

Section: Introductionmentioning

confidence: 99%

An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement

Dikopoulos

Birbas

2022

Chips

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In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs that utilize delay lines. Additionally, this generic method allows for trade-offs between resolution, linearity, and resource utilization. Since nonlinearity is one of the predominant issues regarding delay lines in FPGA-based TDCs, combined with the fact that delay lines are utilized for a wide range of TDC architectures (not limited to the delay-line TDC), other implementations (e.g., Vernier or wave union TDCs), also in different FPGA devices, can directly benefit from the proposed adaptive method, with no need for either custom routing or complex tuning of the converter. Furthermore, implementation-related challenges regarding clock skew, measurement uncertainty, and the placement of the TDC are discussed and we also propose an experimental setup that utilizes only FPGA resources in order to characterize the converter. Although the TDC in this work was implemented in a Xilinx Virtex-6 device and was characterized under different operational modes, we successfully optimized the converter’s nonlinearity and resource utilization while retaining single-shot precision. The best performing (in terms of linearity) implementation reached DNLrms and INLrms values of 0.30 LSB and 0.45 LSB, respectively, and the single-shot precision (σ) was 9.0 ps.

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SAR TDC Architecture with Self-Calibration Employing Trigger Circuit

Cited by 8 publications

References 7 publications

Successive Approximation Analog-to-Digital Converters In Time-Mode Signal Processing

Successive Approximation Analog-to-Digital Converters In Time-Mode Signal Processing

How the Author's Group Came Up with Ideas in Analog/Mixed-Signal Circuit and System Area

An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement

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