Sassy: A Language and Optimizing Compiler for Image Processing on Reconfigurable Computing Systems

Hammes, J.; Draper, Bruce A.; Böhm, A. P. Wim

doi:10.1007/3-540-49256-9_6

Cited by 15 publications

(7 citation statements)

References 14 publications

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“…SA-C or SASSY [19] combines elements of Sisal's array support with a C-like syntax otherwise, the latter very much for the same reasons as SAC. SA-C provides specific support for image processing and explicitly targets reconfigurable computing systems based on FPGAs.…”

Section: Related Workmentioning

confidence: 98%

Implementing the NAS benchmark MG in SAC

Grelck

2002

Proceedings 16th International Parallel and Distributed Processing Symposium

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SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. However, rather than providing a fixed set of builtin array operations, SAC provides means to specify such operations in the language itself in a way that still allows their application to arrays of any dimension and size. This paper illustrates the specificational benefits of this approach by means of a high-level SAC implementation of the NAS benchmark MG realizing 3-dimensional multigrid relaxation with periodic boundary conditions. Despite the high-level approach, experiments show that by means of aggressive compiler optimizations SAC manages to achieve performance characteristics in the range of low-level Fortran and C implementations. For benchmark size class A, SAC is outperformed by the serial Fortran-77reference implementation of the benchmark by only 23%, whereas SAC itself outperforms a C implementation by the same figure. Furthermore, implicit parallelization of the SAC code for shared memory multiprocessors achieves a speedup of 7.6 with 10 processors. With these figures, SAC outperforms both automatic parallelization of the serial Fortran-77 reference implementation as well as an OpenMP solution based on C code.

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Section: Related Workmentioning

confidence: 98%

Implementing the NAS benchmark MG in SAC

Grelck

2002

Proceedings 16th International Parallel and Distributed Processing Symposium

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“…However, the compiler for Sassy [17] (a C subset developed in the CAMERON project) is the only work that explicitly mentions the ability to exploit fine and coarse grain parallelism.…”

Section: A Cad Synthesis Tools and Compilers For Dynamically Reconfimentioning

confidence: 99%

A framework for reconfigurable computing: task scheduling and context management

Maestre

Kurdahi

Fernández

et al. 2001

IEEE Trans. VLSI Syst.

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Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.

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“…To this end, we have developed a high-level language (called SA-C) for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. Together, these tools allow programmers to quickly write algorithms in a high-level language, compile them, and run them on FPGAs.Detailed descriptions of the SA-C language and optimizing compiler can be found elsewhere (see [7,8],or http://www.cs.colostate.edu/~cameron/ for a complete set of documents and publications). This paper only briefly introduces SA-C and its compiler before presenting experiments comparing SA-C programs compiled to a Xilinx XCV-2000E FPGA to equivalent programs running on an 800MHz Pentium III.…”

mentioning

confidence: 99%

Accelerated image processing on FPGAs

Draper

Beveridge

Böhm

et al. 2003

IEEE Trans. on Image Process.

112

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The Cameron project has developed a language called single assignment C (SA-C), and a compiler for mapping image-based applications written in SA-C to field programmable gate arrays (FPGAs). The paper tests this technology by implementing several applications in SA-C and compiling them to an Annapolis Microsystems (AMS) WildStar board with a Xilinx XV2000E FPGA. The performance of these applications on the FPGA is compared to the performance of the same applications written in assembly code or C for an 800 MHz Pentium III. (Although no comparison across processors is perfect, these chips were the first of their respective classes fabricated at 0.18 microns, and are therefore of comparable ages.) We find that applications written in SA-C and compiled to FPGAs are between 8 and 800 times faster than the equivalent program run on the Pentium III.

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Sassy: A Language and Optimizing Compiler for Image Processing on Reconfigurable Computing Systems

Cited by 15 publications

References 14 publications

Implementing the NAS benchmark MG in SAC

Implementing the NAS benchmark MG in SAC

A framework for reconfigurable computing: task scheduling and context management

Accelerated image processing on FPGAs

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