SAT-ATPG using preferences for improved detection of complex defect mechanisms

Abstract

Failures caused by phenomena such as crosstalk or powersupply noise are gaining in importance in advanced nanoscale technologies. The detection of such complex defects benefits from the satisfaction of certain constraints, for instance justifying specific transitions on neighbouring lines of the defect location. We present a SAT-based ATPGtool that supports the enhanced conditional multiple-stuck-at fault model (ECMS@). This model can specify multiple fault locations along with a set of hard conditions imposed on arbitrary lines; hard conditions must hold in order for the fault effect to become active. Additionally, optimisation constraints that may be required for best coverage can be specified via a set of soft conditions. The introduced tool justifies as many of these conditions as possible, using a mechanism known as SAT with preferences. Several applications are discussed and evaluated by extensive experimental data. Furthermore, a novel fault-clustering technique is introduced, thanks to which the time required to classify all stuck-at faults in a suite of industrial benchmarks was reduced by up to 65%.

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

“…As a more generic approach, in the following we present the conditional multiple-stuck-at fault model (CMS@) defined in [13], and an extension thereof the enhanced conditional multiple-stuck-at fault model (ECMS@) [28]. As a further application demonstrating the potential of SAT-based ATPG, we consider ATPG for interconnect open faults.…”

“…Besides testing of resistive bridges [13], applications include ATPG power-droop testing [32], minimization/maximization of fault affected outputs for stuckat faults, and switching activity minimization for transition faults [28].…”

SAT-based ATPG beyond stuck-at fault testing

“…For example the SAT solver Chaff employs the Variable State Independent Decaying Sum (VSIDS) heuristic [34], which has been adopted also by many other solvers. Other strategies to speed up the search process are for example incremental SAT solving or exploiting thread parallelism in the implementation [8,29,38,41,46]. …”

“…The multiple fault analysis can be further improved by incremental SAT-solving [8]. Whenever an unknown fault is combined with a new single fault , then the SATinstance for the multiple fault ⟨ , ⟩ can be built from the SAT-instance for .…”

Search Space Reduction for Low-Power Test Generation

“…In general, the computation time of test generation is depending on the scale and complexity of a circuit. In order to reduce the test generation search space, many methods have been proposed in the last two or three decades [1][2][3][4][5][6].…”