SAT-based algorithm of verification for port order fault

Abstract

In verification of embedded core-based design, Port Order Fault (POF) Model focuses on the errors in connections between the ports of the cores and the surrounding circuits, thus considerably reduces the verification complexity and time. This paper investigated the automatic verification pattern generation for POF, and developed an effective algorithm of verification for POF using SAT instead of BDD. The problem of detecting POF was transformed into SAT, which was efficiently solved by a state-of-art efficient SAT solver.