SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Abstract

Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing.

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs

“…During manufacturing test, power is typically provided from a wall-plugged ATE, and hence battery life is not a concern; however heat dissipation, excessive IR drop, and providing realistic test conditions that mimic functional operation are. Consequently, EDA suppliers have equipped their ATPG tools with low-power modes and pattern compression techniques, in which the switching activity can be constrained by the user, often at the expense of additional test patterns and/or a slight drop in fault coverage [9][10][11][12][13].…”