SAT Based Predicate Abstraction for Hardware Verification

Clarke, Edmund M.; Talupur, Muralidhar; Veith, Helmut; Wang, Dong

doi:10.1007/978-3-540-24605-3_7

Cited by 36 publications

(41 citation statements)

References 19 publications

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“…Our approach, in comparison, builds on top of an existing SAT library and is therefore both straightforward to implement and will immediately benefit from any improvement to the library itself. Nevertheless, we consider the SAT-based algorithm of McMillan to be an important work that has indeed found application in the predicate abstraction of hardware circuits [13] and post-image computation [12]. A variation on the McMillan algorithm is given by Sheng and Hsiao [37] who apply a success-driven rather than a conflict-driven search for models (recall that DPLL-style algorithms use a conflict-driven search).…”

Section: Hybrid Methods and Mcmillan's Methodsmentioning

confidence: 99%

Existential Quantification as Incremental SAT

Brauer

King

Kriener

2011

Computer Aided Verification

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Abstract. This paper presents an elegant algorithm for existential quantifier elimination using incremental SAT solving. This approach contrasts with existing techniques in that it is based solely on manipulating the SAT instance rather than requiring any reengineering of the SAT solver or needing an auxiliary data-structure such as a BDD. The algorithm combines model enumeration with the generation of shortest prime implicants so as to converge onto a quantifier-free formula presented in CNF. We apply the technique to a number of hardware circuits and transfer functions to demonstrate the effectiveness of the method.

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Section: Hybrid Methods and Mcmillan's Methodsmentioning

confidence: 99%

Existential Quantification as Incremental SAT

Brauer

King

Kriener

2011

Computer Aided Verification

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“…In [12], SAT-based predicate abstraction is applied to hardware verification. The authors present two SAT-based algorithms to refine the abstract models.…”

Section: Related Workmentioning

confidence: 99%

“…In [12], a SAT-based technique for predicate abstraction of circuits given in Verilog is introduced. The first step is to obtain predicates from the control flow guards in the Verilog file.…”

Section: Introductionmentioning

confidence: 99%

Predicate Abstraction and Refinement Techniques for Verifying Verilog

Clarke¹,

Jain²,

Kroening³

2004

Self Cite

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Model checking techniques applied to large industrial circuits suffer from the state explosion problem. A major technique to address this problem is abstraction. Predicate abstraction has been applied successfully to large software programs. Applying this technique to hardware designs poses additional challenges. This paper evaluates three techniques to improve the performance of SAT-based predicate abstraction of circuits: 1) We partition the abstraction problem by forming subsets of the predicates. The resulting abstractions are more coarse, but the computation of the abstract transition relation becomes easier. 2) We evaluate the performance effect of lazy abstraction, i.e., the abstraction is only performed if required by a spurious counterexample. 3) We use weakest preconditions of circuit transitions in order to obtain new predicates during refinement. We provide experimental results on publicly available benchmarks from the Texas97 benchmark suite. Report Documentation PageForm Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number.

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“…If not, rather than ruling out only that guess, they determine a reason for that guess not being a solution and rule out guesses doomed to fail for the same reason. Examples are verification with CEGAR (e.g., [20]) and SMT (e.g., [47]). Automated support for determining a reason for unsatisfiability is clearly essential.…”

Section: Introductionmentioning

confidence: 99%

Towards a Notion of Unsatisfiable Cores for LTL

Schuppan¹

2010

Fundamentals of Software Engineering

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Abstract. Unsatisfiable cores, i.e., parts of an unsatisfiable formula that are themselves unsatisfiable, have important uses in debugging specifications, speeding up search in model checking or SMT, and generating certificates of unsatisfiability. While unsatisfiable cores have been well investigated for Boolean SAT and constraint programming, the notion of unsatisfiable cores for temporal logics such as LTL has not received much attention. In this paper we investigate notions of unsatisfiable cores for LTL that arise from the syntax tree of an LTL formula, from converting it into a conjunctive normal form, and from proofs of its unsatisfiability. The resulting notions are more fine-granular than existing ones.

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SAT Based Predicate Abstraction for Hardware Verification

Cited by 36 publications

References 19 publications

Existential Quantification as Incremental SAT

Existential Quantification as Incremental SAT

Predicate Abstraction and Refinement Techniques for Verifying Verilog

Towards a Notion of Unsatisfiable Cores for LTL

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