SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays

Anderson, I.D.L.; Khalid, Mohammed

doi:10.1049/iet-cdt:20070120

Cited by 9 publications

(6 citation statements)

References 12 publications

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“…Various trends in custom processor design have been investigated in the literature. Tensilica Xtensa [1], MetaCore [12, 13] and SC build [13] are some examples of partially customisable processor environments in which the main body of the processor is fixed, while a limited number of elements or components are left customisable. ADLs such as PEAS III [14], LISA [15] and EXPRESSION [16] offer designing from scratch, which provides higher flexibility by allowing the designers to define their own instruction‐set architecture (ISA) and datapath at the expense of more design complexity.…”

Section: Related Workmentioning

confidence: 99%

Accuracy‐aware processor customisation for fixed‐point arithmetic

Vakili¹,

Langlois²,

Bois³

2016

IET Computers & Digital Techniques

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Section: Related Workmentioning

confidence: 99%

Accuracy‐aware processor customisation for fixed‐point arithmetic

Vakili¹,

Langlois²,

Bois³

2016

IET Computers & Digital Techniques

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“…There are two basic trends in application‐specific custom processor design: partial customisation of a configurable processor and designing from scratch. Tensilica Xtensa [6], MetaCore [10], SC Build [11] are some examples of partially customisable processor environment in which the main body of the processor is fixed, while a limited number of elements or components are left customisable. ADLs such as PEAS III [12], LISA [13] and EXPRESSION [5] offer designing from scratch, which provides higher flexibility by allowing the designers to define their own ISA and datapath at the expense of more design complexity.…”

Section: Related Workmentioning

confidence: 99%

Customised soft processor design: a compromise between architecture description languages and parameterisable processors

Vakili¹,

Langlois²,

Bois³

2013

IET Computers & Digital Techniques

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Processor customisation is an effective technique to enhance performance across an application domain. In this study, the authors present a new customised soft processor development environment called polytechnique customised soft processor (PolyCuSP), which bridges the gap between architecture description languages (ADLs) and extensible soft processors. The main objective of this environment is to facilitate rapid design space exploration while preserving a wide range of customisation flexibility. For this purpose, PolyCuSP offers full flexibility in instruction-set description, while limiting the datapath customisation to a predefined set of tunable microarchitectural parameters. The environment avoids extensive datapath description that is unnecessary for usual microarchitectural customisation techniques in order to simplify the development process. A new XML-based description format is introduced for instruction-set modelling. Experimental results evaluate and compare the design and customisation complexities offered by PolyCuSP with competitive approaches. Results demonstrate the efficiency of applying customisation techniques in the proposed environment. For the Sobel edge detection algorithm, the results show that microarchitectural tuning and instruction-set architecture customisation improve the performance-per-cost ratio by an average of 44 and 27%, respectively. Furthermore, in a case study of a tone-mapping algorithm, PolyCuSP achieves an average improvement of 38% in performance-per-cost ratio over an ADL-based design applying the same customisations.

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“…Early estimators of area and delay for field programmable gate array (FPGA) implementations were used in [4] to evaluate the design space before any behavioural synthesis. Anderson et al [5] collect system information before the exploration starts doing a configuration sweep and use a GA for the exploration of a parameterised reduced instruction set computer (RISC) processor. A compiler approach to perform hardware DSE is presented in [6] where parallelisation techniques are used to map computations to FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Machine learning predictive modelling high-level synthesis design space exploration

Schafer

Wakabayashi

2012

IET Comput. Digit. Tech.

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A machine learning-based predictive model design space exploration (DSE) method for high-level synthesis (HLS) is presented. The method creates a predictive model for a training set until a given error threshold is reached and then continues with the exploration using the predictive model avoiding time-consuming synthesis and simulations of new configurations. Results show that the authors' method is on average 1.92 times faster than a genetic-algorithm DSE method generating comparable results, whereas it achieves better results when constraining the DSE runtime. When compared with a previously developed simulated annealer (SA)-based method, the proposed method is on average 2.09 faster, although again achieving comparable results.

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SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays

Cited by 9 publications

References 12 publications

Accuracy‐aware processor customisation for fixed‐point arithmetic

Accuracy‐aware processor customisation for fixed‐point arithmetic

Customised soft processor design: a compromise between architecture description languages and parameterisable processors

Machine learning predictive modelling high-level synthesis design space exploration

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