Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA

Rakossy, Zoltan Endre; Stengele, Dominik; Acosta-Aponte, Axel; Chafekar, Saumitra; Bientinesi, Paolo; Chattopadhyay, Anupam

doi:10.1007/978-3-319-16214-0_25

Cited by 6 publications

(9 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Considering the overall performance, our implementation is clearly superior by several orders of magnitude, though, the comparison is not accurate as the performance measured for Layers is for a stand-alone core without considering complete system integration and communication latency with a host CPU. [139]…”

Section: Dsp Gpgpu and Fpga Aggregated Resultsmentioning

confidence: 99%

“…Focus is kept on efficiency and scalability during the case studies, covering a wide range of possible requirements, highlighting the flexibility of this approach. The chapter is based on my work from several publications [135][136][137][138][139][140] 1 , treating different aspects of this exploration.…”

Section: Chaptermentioning

confidence: 99%

“…Repeating such iterations will reduce to a 2 × 2 or 3 × 3 special case, which finally yield the final result in one element. [139] The procedure is repeated until the folding front reaches a 2 × 2 or a 3 × 3 data square, shown in Fig. 6.7.…”

Section: Mappingmentioning

confidence: 99%

“…X denotes taking previous output (self). [139] From the language perspective, there are no special requirements: multiplication and addition are alternating, which is basic elementary function of the layer 0. Combined with the source functions, data can be received and sent to layer 1 easily.…”

Section: Dot Mappingmentioning

confidence: 99%

“…Largest designs have significant area increase due to bigger multiplexer and decode logic structures (3-bit → 4-bit) and significant frequency penalty due to long L1 wires. [139] memory bandwidth, especially when requiring a divider. When comparing to the clean version of Layers, it is interesting to note that the reconfigurable control path slows the architecture down, although by not operating near maximum frequency has great advantages in power consumption (Table 6.1).…”

Section: Time Energy and Scalabilitymentioning

confidence: 99%

See 4 more Smart Citations

Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

View full text Add to dashboard Cite

Current trends in architectural design require high-performance, low-power, flexible architectures that can adapt quickly onto the ever shifting and evolving application landscape. Finding the best architecture matching these stringent constraints is further limited by a short time-to-market window, which severely limits design exploration options. This work tackles these problems by proposing a different view on architectural flexibility, which can be exploited to achieve high energy-efficiency and performance instead of being traded off, by exploiting the advantages of reconfigurable architectures. Starting from a theoretical view, a methodology is produced for exploration of two different approaches in achieving high energy efficiency with two different architectural concepts: an architecture perfectly tuned to the application; and a new reconfigurable layered architecture, which can adapt its structure to match the application.

show abstract

Section: Dsp Gpgpu and Fpga Aggregated Resultsmentioning

confidence: 99%