Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases

Wirth, Johannes; Hofmann, Jaco; Thostrup, Lasse; Binnig, Carsten; Koch, Andreas

doi:10.1109/icfpt52863.2021.9609804

Cited by 2 publications

(2 citation statements)

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“…The majority of the recent HBM-based accelerators [19], [20], [23] are HLS designs but are not able to get more than 190 MHz and use more than 28 HBM channels. [21] implements a hash join accelerator that uses 32 HBM channels while running at 250 MHz and its random memory accesses are through 256-bit wide AXI interfaces. However, using a 256-bit wide AXI interface can only utilize half of the available HBM bandwidth at most.…”

Section: Related Workmentioning

confidence: 99%

“…Finally, the HBM stacks are physically connected to a datacenter FPGA's bottom die only, making it difficult to spread the resource utilization across multiple FPGA dies to achieve desirable timing closure. To the best of our knowledge, none of the published HBM-based accelerator designs [19], [20], [21], [22], [23] is able to fully utilize the entire bandwidth of the 32 HBM channels.…”

Section: Introductionmentioning

confidence: 99%

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TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs

Qiao¹,

Guo²,

Fang³

et al. 2022

Preprint

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The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available off-chip memory bandwidth. However, it is nontrivial for designers to fully utilize this immense bandwidth. First, the existing sorter designs cannot be directly scaled at the increasing rate of available off-chip bandwidth, as the required on-chip resource usage grows at a much faster rate and would bound the sorting performance in turn. Second, designers need an in-depth understanding of HBM's characteristics to effectively utilize the HBM bandwidth. To tackle these challenges, we present TopSort, a novel two-phase sorting solution optimized for HBM-based FPGAs. In the first phase, 16 merge trees work in parallel to fully utilize 32 HBM channels' bandwidth. In the second phase, TopSort reuses the logic from phase one to form a wider merge tree to merge the partially sorted results from phase one. TopSort also adopts HBM-specific optimizations to reduce resource overhead and improve bandwidth utilization. TopSort can sort up to 4 GB data using all 32 HBM channels, with an overall sorting performance of 15.6 GB/s. TopSort is 6.7× and 2.2× faster than state-of-the-art CPU and FPGA sorters.

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