Scalable and modular pervasive logic/firmware design

Webel, Tobias; Pflueger, T.; Ludewig, R.; Lichtenau, Cedric; Niklaus, W.; Schaufler, R.

doi:10.1147/jrd.2011.2177571

Cited by 6 publications

(2 citation statements)

References 10 publications

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“…These features have been implemented for many chip generations by a design group calling themselves the Pervasive Design Community. The logic implements a layered, hierarchical base architecuture [4]. This architecture allows an external serPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro↓t or commercial advantage and that copies bear this notice and the full citation on the ↓rst page.…”

Section: Pervasive Designmentioning

confidence: 99%

Verification of Non-Mainline Functions in Todays Processor Chips

Koesters

Goryachev

2014

Proceedings of the 51st Annual Design Automation Conference

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In a modern chip development cycle non-mainline / nonfunctional verification is gaining importance compared to traditional functional verification tasks and takes up to one third of the total verification effort. The purpose of nonmainline logic is to operate, maintain, and debug the chip. Ever-increasing complexity of the chip, thus, directly affects the complexity of the non-mainline logic and as a result, the verification thereof. Moreover, the non-mainline world is no longer pure hardware, but an intricate mix of software and hardware.We claim that traditional constrained-random verification methods are not valid for the non-mainline domain and the verification should be based on usage scenarios. Moreover, these scenarios must be formally specified to avoid ambiguity and allow collaboration of different teams involved in the chip development.

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Section: Pervasive Designmentioning

confidence: 99%

Verification of Non-Mainline Functions in Todays Processor Chips

Koesters

Goryachev

2014

Proceedings of the 51st Annual Design Automation Conference

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“…Such parameters are, for example, the amount of processors and processing cores as well as memory and I/O configuration [7,8]. A chip initialization sequence is being developed by hardware development teams at the same time the hardware design of the z System processor takes place.…”

Section: Introducing a Virtual Self-boot Engine For Improved Chip Inimentioning

confidence: 99%

Innovations in infrastructure firmware for the IBM z13

et al. 2015

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A built-in BTI monitor for long-term data collection in IBM microprocessors

Jenkins

2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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A circuit for long-term measurement of bias temperature instability (BTI) degradation is described. It is an entirely on-chip measurement circuit, which reports measurements periodically with a digital output. Implemented on IBM's z196 Enterprise systems, it can be used to monitor longterm degradation under real-use conditions. Over 500 days worth of ring oscillator degradation data from customer systems are presented. The importance of using a reference oscillator to measure performance degradation in the field, where the supply voltage and temperature can vary dynamically, is shown.

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Scalable and modular pervasive logic/firmware design

Cited by 6 publications

References 10 publications

Verification of Non-Mainline Functions in Todays Processor Chips

Verification of Non-Mainline Functions in Todays Processor Chips

Innovations in infrastructure firmware for the IBM z13

A built-in BTI monitor for long-term data collection in IBM microprocessors

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