Scalable Effort Hardware Design

Abstract

Applications from several application domains exhibit the property of inherent application resilience, offering entirely new avenues for performance and power optimization by relaxing the conventional requirement of exact (numerical or Boolean) equivalence between the specification and hardware implementation. We propose scalable effort hardware as a design approach to tap the reservoir of application resilience and translate it into highly efficient hardware implementations. The first tenet of the scalable effort design approach is to identify mechanisms at each level of design abstraction (circuit, architecture, and algorithm) that can be used to vary the computational effort expended toward generation of the correct (exact) result, and to expose these mechanisms as control knobs in the implementation. These scaling mechanisms can be utilized to achieve improved energy efficiency while maintaining an acceptable (and often, near identical) level of quality of the overall result. The second tenet of the scalable effort design approach is that fully exploiting the potential of application resilience requires synergistic cross-layer optimization of scaling mechanisms identified at different levels of design abstraction. We have implemented an energy-efficient recognition and mining (RM) processor based on the proposed scalable effort design approach. Results from the execution of support vector machine training and classification, generalized learning vector quantization training, and k-means clustering on the scalable effort RM processor show that it can achieve energy reductions of 1.2×-5× with negligible impact on output quality, and 2.2×-50× with moderate loss in output quality, across various data sets. Our results also establish that cross-layer optimization across different scaling mechanisms leads to higher energy savings (1.4×-2× on an average) for a given output quality compared with each of the individual techniques.

Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems

“…The first approach is based on designing circuits in over-scaled conditions (voltage) to achieve large improvements in energy, albeit with some (controlled) accuracy degradation. However, over-scaling can have a lasting impact on the MSBs resulting in unacceptable performance loss [15]. The second approach approximates the fundamental logic functions so as to reduce the hardware complexity (deviation from precise specification with few transistors or gates [16][17][18][19][20]) thereby achieving area and energy benefits.…”

Scalable-effort classifiers for energy-efficient machine learning

“…The first approach is to design circuits that operate under overscaled conditions (timing/voltage), leading to timing-induced errors. The key challenge in this approach is to mitigate the natural tendency of overscaling to impact the most significant bits, resulting in an unacceptable loss in quality [24]. Techniques to alleviate the impact of timing errors and obtain a more graceful degradation in quality were proposed in [25][26][27][28][29].…”

“…Architectural design techniques for approximate computing can be investigated in the context of a spectrum of architectures, ranging from application-specific accelerators to fully programmable processors. In the case of specialized hardware accelerators, significance-driven computation [36] and scalable e↵ort hardware design [24,[37][38][39][40][41] can lead to highly energy e cient implementations. The key principles are to ensure that computations are approximated based on their significance in determining output quality, and to design hardware to be scalable-e↵ort, i.e., to expose knobs that regulate quality-e ciency trade-o↵s, so that the hardware can be operated at any desired quality point.…”

“…For instance, in the context of a hardware accelerator for recognition and mining, an additional 1.4X-2X energy savings is achieved when approximations are introduced together across the algorithm, architecture and circuit levels, as compared to the case where approximations are restricted to any single level [24].…”

Approximate computing for efficient information processing

“…The key challenge is to mitigate the natural tendency of overscaling to impact the most significant bits, resulting in unacceptable loss in quality [13]. Alternatively, functionally approximate circuits can be designed that deviate from the golden specification but contain fewer transistors or gates [14]- [17].…”