Scalable FPGA graph model to detect routing faults

Sterpone, Luca; Cabodi, Gianpiero; Finocchiaro, S.F.; Loiacono, Carmelo; Savarese, Francesco; Du, Boyang

doi:10.1109/iolts.2016.7604690

Cited by 1 publication

(1 citation statement)

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“…As depicted in Fig. 3, there are several situations in a switch box (SB), where one SEU induces multiple errors violating the single fault assumption [20]. In particular, an upset in the configuration frame of the SB changes the connection layout, producing a conflict between two nets and unpredictable behaviors in the carried logic value.…”

Section: A Backgroundmentioning

confidence: 99%

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs

Sterpone

Boragno

2017

2017 IEEE 23rd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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SRAM-Based FPGAs represent a low-cost alternative to ASIC device thanks to their high performance and design flexibility. In particular, for aerospace and avionics application fields, SRAM-based FPGAs are increasingly adopted for their configurability features making them a viable solution for long-time applications. However, these fields are characterized by a radiation environment that makes the technology extremely sensitive to radiation-induced Single Event Upsets (SEUs) in the SRAM-based FPGA's configuration memory. Configuration scrubbing and Triple Modular Redundancy (TMR) have been widely adopted in order to cope with SEU effects. However, modern FPGA devices are characterized by a heterogeneous routing resource distribution and a complex configuration memory mapping causing an increasing sensitivity to Cross Domain Errors affecting the TMR structure. In this paper we developed a new methodology to calculate the reliability of TMR architecture considering the intrinsic characteristics of the new generation of SRAM-based FPGAs. The method includes the analysis of the configuration bit sharing phenomena and of the routing long lines. We experimentally evaluate the method of various benchmark circuits evaluating the Mean Upset To Failure (MUTF). Finally, we used the results of the developed method to implement an improved design achieving 29x improvement of the MUTF.

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Section: A Backgroundmentioning

confidence: 99%