Scalable Hardware Architecture for fast Gradient Boosted Tree Training

Abstract

Gradient Boosted Tree is a powerful machine learning method that supports both classification and regression, and is widely used in fields requiring high-precision prediction, particularly for various types of tabular data sets. Owing to the recent increase in data size, the number of attributes, and the demand for frequent model updates, a fast and efficient training is required. FPGA is suitable for acceleration with power efficiency because it can realize a domain specific hardware architecture; however it is necessary to flexibly support many hyper-parameters to adapt to various dataset sizes, dataset properties, and system limitations such as memory capacity and logic capacity. We introduce a fully pipelined hardware implementation of Gradient Boosted Tree training and a design framework that enables a versatile hardware system description with high performance and flexibility to realize highly parameterized machine learning models. Experimental results show that our FPGA implementation achieves a 11-to 33-times faster performance and more than 300-times higher power efficiency than a state-of-the-art GPU accelerated software implementation.

Warning of Dangerous Driving Behavior Caused by Drivers and Road Environmental Factors

“…After desensitization and structured data processing, we have selected the "weather", "time (hours)", "time (week)", "time (months)", "emotion", "fatigue" and "speed" and "accident" eight fields, and use the gradient promotion training tree algorithm of data and model building [12]. Finally, the prediction accuracy of training set and test set reached 82.20% and 81.69% respectively [13].…”