Scalable Integer DCT Architecture for HEVC Encoder

Abdelrasoul, Maher; Sayed, Mohammed S.; Goulart, Victor

doi:10.1109/isvlsi.2016.98

Cited by 9 publications

(5 citation statements)

References 13 publications

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“…FPGA-based solutions for Intra coding are presented in [7,8]. Architectures for HEVC standard DCT acceleration introduced in [9][10][11][12] show several different approaches for optimizing integer based DCT. Interpolation [13] and deblocking filter [14] as another compute demanding algorithms are also subject of the research in this area.…”

Section: Motivation and Related Workmentioning

confidence: 99%

Performance-efficient integration and programming approach of DCT accelerator for HEVC in MANGO platform

2019

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Video encoding based on novel HEVC standard is an extremely computationally expensive process and achieving efficient encoding requires intelligent utilization of all available resources, from both software and hardware perspective. Profiling and analysis of the encoding process identified Discrete cosine transform (DCT) as one of the key kernels that consume most of the time in the application's runtime. Therefore, high-throughput, fully-pipelined hardware accelerator was designed in FPGA and integrated into MANGO platform. MANGO platform is heterogeneous HPC system that consists of different types of nodes, from general purpose nodes (GN) to heterogeneous nodes (HN). While executing specific kernels on GN nodes is a straightforward process, executing kernels on accelerator-based HNs is a more complex procedure and requires specific integration to successfully exploit heterogeneous architecture. This paper presents performance-efficient integration of DCT hardware accelerator in MANGO platform, focusing on the performance of the encoder while maintaining coding efficiency and video quality of the encoded bitstream. Several approaches were considered, tested and compared; from the standalone integration where series of single tasks were offloaded to the DCT accelerator, to more complex solutions based on smart buffer utilization.

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Section: Motivation and Related Workmentioning

confidence: 99%

Performance-efficient integration and programming approach of DCT accelerator for HEVC in MANGO platform

2019

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“…Re-synthesis is performed as described in Section IV-A and accounts for all currently considered bitwidths thanks to MCMM. The energy of the resulting circuit is evaluated again using Equation (1) in line 15.…”

Section: Optimal V Dd Selectionmentioning

confidence: 99%

“…After reading the scenario independent constraints (line 8), the script now overrides the clock period definition in each scenario, multiplying the period by the appropriate factor (lines 11-13). Finally, case analysis constraints are set by simply applying the specified values to all the control inputs defined in the target_scenarios (lines [15][16][17][18][19][20]. In practice, our tool uses a single TCL script to generate scenarios, and discerns between DVAFS and DVAS depending on the presence/absence of clock multipliers and control inputs definitions in the input list.…”

Section: Support For Dvafsmentioning

confidence: 99%

Automated Synthesis of Energy-Efficient Reconfigurable-Precision Circuits

2019

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In recent years, designers are trying to move part of the computing tasks involved in Internet of Things applications from the cloud to the edge. This imposes increasing performance demands on edge nodes, which usually clash with their limited energy budget. An effective workaround is to leverage hardware capable of varying its computational precision at runtime, which can provide ''good-enough'' results while significantly reducing energy consumption. Dynamic Voltage and Accuracy Scaling (DVAS) and its variants are particularly promising methods to implement such hardware, due to their general applicability and contained overheads. However, these methods are negatively affected by the optimizations performed by commercial Electronic Design Automation (EDA) tools. As a consequence, when applied within a standard design flow, they do not yield the expected results. This paper describes a synthesis tool that solves this issue, allowing the integration of reconfigurable-precision circuits based on DVAS in standard design flows based on commercial tools. Moreover, our tool can receive information about the relevance of different precisions for the target application(s) that will use the circuit, and further optimize the design accordingly. When applied to two realistic use cases (neural network inference and image compression), our tool reduces the total energy consumption of reconfigurable-precision circuits of 20-25% compared to a straight-forward application of DVAS.

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“…Therefore, there are a few publications detailing the hardware implementations of the DCT transforms to fulfil the requirements of the standard. Most of the existing works focus on implementing either DCT circuit [7][8][9][10][11][12][13] or IDCT circuit [14][15][16][17][18]. In [7] three flexible architectures were proposed to perform one-dimensional (1D)-DCT operation for any DCT size focusing on the reusability and flexibility that allow one design to do more than one function.…”

Section: Related Workmentioning

confidence: 99%

“…It makes use of matrix multiplication decomposition based on transform division into fixed‐size blocks to reduce the size of transformation buffer. In [13], a scalable integer DCT architecture based on matrix decomposition and optimised multiplication circuit has been proposed. A field‐programmable gate array implementation of HEVC 2D IDCT algorithm using high‐level synthesis tools was proposed in [14].…”

Section: Related Workmentioning

confidence: 99%

Real‐time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

Abdelrasoul

Sayed

Goulart

2017

IET Circuits, Devices & Systems

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In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT.

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Scalable Integer DCT Architecture for HEVC Encoder

Cited by 9 publications

References 13 publications

Performance-efficient integration and programming approach of DCT accelerator for HEVC in MANGO platform

Performance-efficient integration and programming approach of DCT accelerator for HEVC in MANGO platform

Automated Synthesis of Energy-Efficient Reconfigurable-Precision Circuits

Real‐time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

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