Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors

Abstract

Modern multicore systems are migrating from homogeneous systems to heterogeneous systems with accelerator-based computing in order to overcome the barriers of performance and power walls. In this trend, FPGA-based accelerators are becoming increasingly attractive, due to their excellent flexibility and low design cost. In this paper, we propose the architectural support for efficient interfacing between FPGA-based multi-accelerators and chip-multiprocessors (CMPs) connected through the network-on-chip (NoC). Distributed packet receivers and hierarchical packet senders are designed to maintain scalability and reduce the critical path delay under a heavy task load. A dedicated accelerator chaining mechanism is also proposed to facilitate intra-FPGA data reuse among accelerators to circumvent prohibitive communication overhead between the FPGA and processors. In order to evaluate the proposed architecture, a complete system emulation with programmability support is performed using FPGA prototyping. Experimental results demonstrate that the proposed architecture has high-performance, and is lightweight and scalable in characteristics.

FPGA Implementation for the Sigmoid with Piecewise Linear Fitting Method Based on Curvature Analysis

“…These hardware platforms include embedded devices, Internet of Things (IoT) applications, and field-programmable gate array (FPGA) boards [4,5]. It is also necessary to strike a balance between performance and functional flexibility when realizing a feasible neural network model design [6,7].…”