Scalable methods for the analysis and optimization of gate oxide breakdown

Fang, Jianxin; Sapatnekar, Sachin S.

doi:10.1109/isqed.2010.5450507

Cited by 4 publications

(2 citation statements)

References 13 publications

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“…Ageing also one of the important concerns for PUF circuits. As the continuous utilization of the CMOS devices which leads to a progressive degradability of the system performance and the mechanisms which alters the performance of CMOS devices are Negative bias temperature instability (NBTI), Hot Carrier Injection (HCI), temperature dependent die electric break ISSN: 2089-3272  A secure arbiter physical unclonable functions (PUFs) for device authentication … (Anil Kumar Kurra) 119 down (TDDB), positive bias temperature instability (PBTI), electro migration and soft errors are consider as a major causes to alter the properties of a ICs [10]- [12].…”

Section: Mtotal= Mglobal+mlocalmentioning

confidence: 99%

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

Kurra¹,

Nelakuditi²

2019

IJEEI

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Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.

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Section: Mtotal= Mglobal+mlocalmentioning

confidence: 99%

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

Kurra¹,

Nelakuditi²

2019

IJEEI

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“…This enables the indirect quantification of border traps generated during a TDDB degradation test. Furthermore, the enhanced model presented here can be used to inspect, through circuit simulations, the impact of the thin oxide degradation on the performance of analog and digital circuits using well-known methodologies such as those presented in [26,27]. This aids in predicting the conditions that might yield critical damage on actual circuits used at radiofrequencies [19].…”

Section: Introductionmentioning

confidence: 99%

RC-Effects on the Oxide of SOI MOSFET under Off-State TDDB Degradation: RF Characterization and Modeling

Otero-Carrascal,

Chaparro-Ortiz,

Srinivasan

et al. 2024

Micromachines

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Based on S-parameter measurements, the effect of dynamic trapping and de-trapping of charge in the gate oxide, the increase of dielectric loss due to polarization, and the impact of leakage current on the small-signal input impedance at RF is analyzed and represented. This is achieved by systematically extracting the corresponding model parameters from single device measurements at different frequency ranges, and then the methodology is applied to analyze the evolution of these parameters when the device is submitted to non-conducting electrical stress. This approach not only allows to inspect the impact of effects not occurring under DC conditions, such as the current due to the time varying dielectric polarization, but also to clearly distinguish effects in accordance with the functional form of their contribution to the device’s impedance. In fact, it is shown that minor changes in the model of the gate capacitance by including additional resistive and capacitive components allows for an excellent model-experiment correlation up to 30 GHz. Moreover, the accuracy of the correlation is shown to be maintained when applying the proposal to the device under different gate-to-source bias conditions and at several stages during off-state degradation.

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Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits

Lee

Kim

2011

2011 International SoC Design Conference

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Scalable methods for the analysis and optimization of gate oxide breakdown

Cited by 4 publications

References 13 publications

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

RC-Effects on the Oxide of SOI MOSFET under Off-State TDDB Degradation: RF Characterization and Modeling

Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits

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