Scalable NoC-based Neuromorphic Hardware Learning and Inference

Abstract

Bio-inspired neuromorphic hardware is a research direction to approach brain's computational power and energy efficiency. Spiking neural networks (SNN) encode information as sparsely distributed spike trains and employ spike-timingdependent plasticity (STDP) mechanism for learning. Existing hardware implementations of SNN are limited in scale or do not have in-hardware learning capability. In this work, we propose a low-cost scalable Network-on-Chip (NoC) based SNN hardware architecture with fully distributed in-hardware STDP learning capability. All hardware neurons work in parallel and communicate through the NoC. This enables chip-level interconnection, scalability and reconfigurability necessary for deploying different applications. The hardware is applied to learn MNIST digits as an evaluation of its learning capability. We explore the design space to study the trade-offs between speed, area and energy. How to use this procedure to find optimal architecture configuration is also discussed.

An ASIC Architecture With Inter-Chip Networking for Individual Control of Adaptive-Metamaterial Cells

“…With the advent of reconfigurable processors and software defined networking [1], there have been many architectures [2]− [6] that provide flexibility and energy efficiency in network systems. Recently, Network-on-Chip (NoC) systems have been established as the dominant communication method in multicore processors, mostly because of their increased scalability [7]− [9]. However, until now, there has been limited availability of networked-IC solutions to address the needs for programmable metamaterials and programmable metasurfaces (MSFs).…”

An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM

“…To achieve high performance and energy efficiency, hardware acceleration of DNNs is intensively studied both in academia and industry [2][3][4][5][6][7][8][9]. DNN model compression techniques, including weight pruning [10][11][12][13][14][15] and weight quantization [16][17][18], are developed to facilitate hardware acceleration by reducing storage/computation in DNN inference with negligible impact on accuracy.…”