Scalable set of reversible parity gates for integer factorization

Abstract

Classical microprocessors operate on irreversible gates, that, when combined with , half-adder and full-adder operations, execute complex tasks such as multiplication of integers. We introduce parity versions of all components of a multiplication circuit. The parity gates are reversible quantum gates based on the recently introduced parity transformation and build on ground-space encoding of the corresponding gate logic. Using a quantum optimization heuristic, e.g., an adiabatic quantum computing protocol, allows one to quantum mechanically reverse the process of multiplication and thus factor integers, which has applications in cryptography. Our parity approach builds on nearest-neighbor constraints equipped with local fields, able to encode the logic of a binary multiplication circuit in a modular and scalable way.