Scalable SIMD-Efficient Graph Processing on GPUs

Khorasani, Farzad; Gupta, Rajiv; Bhuyan, Laxmi N.

doi:10.1109/pact.2015.15

Cited by 113 publications

(59 citation statements)

References 19 publications

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“…Gianinazzi et al report a running time of 5 seconds for RMAT graphs with n = 16000 and an average degree of 4000, using 1536 cores. As NOI can find the minimum cut on RMAT graphs [19] of equal size in less than 2 seconds using a single core, we do not include the implementation in [9] in our experiments.…”

Section: Experiments and Resultsmentioning

confidence: 99%

Shared-Memory Exact Minimum Cuts

Henzinger

Noe

Schulz

2019

2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

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The minimum cut problem for an undirected edgeweighted graph asks us to divide its set of nodes into two blocks while minimizing the weight sum of the cut edges. In this paper, we engineer the fastest known exact algorithm for the problem.State-of-the-art algorithms like the algorithm of Padberg and Rinaldi or the algorithm of Nagamochi, Ono and Ibaraki identify edges that can be contracted to reduce the graph size such that at least one minimum cut is maintained in the contracted graph. Our algorithm achieves improvements in running time over these algorithms by a multitude of techniques. First, we use a recently developed fast and parallel inexact minimum cut algorithm to obtain a better bound for the problem. Then we use reductions that depend on this bound, to reduce the size of the graph much faster than previously possible. We use improved data structures to further improve the running time of our algorithm. Additionally, we parallelize the contraction routines of Nagamochi, Ono and Ibaraki. Overall, we arrive at a system that outperforms the fastest stateof-the-art solvers for the exact minimum cut problem significantly.

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Section: Experiments and Resultsmentioning

confidence: 99%

Shared-Memory Exact Minimum Cuts

Henzinger

Noe

Schulz

2019

2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

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“…But there are no well-known tools for generating such graphs. So we first generate a powerlaw graph using the parallel RMAT tool [35], and develop a custom tool to add additional edges between vertices that have an odd degree, to make the graph Eulerian. The tool ensures that the edge degree distribution of the modified graph closely matches the original graph, as illustrated in Fig.…”

Section: Experiments Setupmentioning

confidence: 99%

A Partition-Centric Distributed Algorithm for Identifying Euler Circuits in Large Graphs

Simmhan

2019

2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Finding the Eulerian circuit in graphs is a classic problem, but inadequately explored for parallel computation. With such cycles finding use in neuroscience and Internet of Things for large graphs, designing a distributed algorithm for finding the Euler circuit is important. Existing parallel algorithms are impractical for commodity clusters and Clouds. We propose a novel partition-centric algorithm to find the Euler circuit, over large graphs partitioned across distributed machines and executed iteratively using a Bulk Synchronous Parallel (BSP) model. The algorithm finds partial paths and cycles within each partition, and refines these into longer paths by recursively merging the partitions. We describe the algorithm, analyze its complexity, validate it on Apache Spark for large graphs, and offer experimental results. We also identify memory bottlenecks in the algorithm and propose an enhanced design to address it. * 2. We implement the algorithm on Apache Spark [23], and present experimental results and analysis for large synthetic graphs, in Sec. 4.3. We identify memory bottlenecks in our design and propose improvements,

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“…In the following sections, we focus our evaluation on the matrices shown in Table I, which are representative of the suite and highlight the most interesting performance characteristics. All matrices were obtained from the University of Florida Sparse Matrix Collection [7] with the exception of rmat, which is an RMAT graph that was generated with RMAT a, b and c parameters of 0.45, 0.22 and 0.22, respectively [8]. For the symmetric matrices, we store and operate on the entire matrix rather than just the upper or lower triangular matrix.…”

Section: A Experimental Setupmentioning

confidence: 99%

Impact of Traditional Sparse Optimizations on a Migratory Thread Architecture

Rolinger

Krieger

2018

2018 IEEE/ACM 8th Workshop on Irregular Applications: Architectures and Algorithms (IA3)

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Achieving high performance for sparse applications is challenging due to irregular access patterns and weak locality. These properties preclude many static optimizations and degrade cache performance on traditional systems. To address these challenges, novel systems such as the Emu architecture have been proposed. The Emu design uses light-weight migratory threads, narrow memory, and near-memory processing capabilities to address weak locality and reduce the total load on the memory system. Because the Emu architecture is fundamentally different than cache based hierarchical memory systems, it is crucial to understand the cost-benefit tradeoffs of standard sparse algorithm optimizations on Emu hardware. In this work, we explore sparse matrix-vector multiplication (SpMV) on the Emu architecture. We investigate the effects of different sparse optimizations such as dense vector data layouts, work distributions, and matrix reorderings. Our study finds that initially distributing work evenly across the system is inadequate to maintain load balancing over time due to the migratory nature of Emu threads. In severe cases, matrix sparsity patterns produce hot-spots as many migratory threads converge on a single resource. We demonstrate that known matrix reordering techniques can improve SpMV performance on the Emu architecture by as much as 70% by encouraging more consistent load balancing. This can be compared with a performance gain of no more than 16% on a cache-memory based system.

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Scalable SIMD-Efficient Graph Processing on GPUs

Cited by 113 publications

References 19 publications

Shared-Memory Exact Minimum Cuts

Shared-Memory Exact Minimum Cuts

A Partition-Centric Distributed Algorithm for Identifying Euler Circuits in Large Graphs

Impact of Traditional Sparse Optimizations on a Migratory Thread Architecture

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