Architectures for Networking and Communications Systems 2013
DOI: 10.1109/ancs.2013.6665177
|View full text |Cite
|
Sign up to set email alerts
|

Scalable Ternary Content Addressable Memory implementation using FPGAs

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
69
0

Year Published

2014
2014
2024
2024

Publication Types

Select...
3
3
2

Relationship

1
7

Authors

Journals

citations
Cited by 76 publications
(69 citation statements)
references
References 13 publications
0
69
0
Order By: Relevance
“…All tables (State, Port, SAR) and Timers hold one entry per connection as discussed in section IV, therefore they scale linearly. Further, the session lookup data structure also scales linearly with the number of sessions as has been shown in [20]. Thus, scaling is linear with number of supported sessions and limited by the amount of BRAM inside the FPGA while LUT and FlipFlop usage will remain mostly constant.…”
Section: ) 10 Gbps Line-rate Supportmentioning
confidence: 95%
See 1 more Smart Citation
“…All tables (State, Port, SAR) and Timers hold one entry per connection as discussed in section IV, therefore they scale linearly. Further, the session lookup data structure also scales linearly with the number of sessions as has been shown in [20]. Thus, scaling is linear with number of supported sessions and limited by the amount of BRAM inside the FPGA while LUT and FlipFlop usage will remain mostly constant.…”
Section: ) 10 Gbps Line-rate Supportmentioning
confidence: 95%
“…At the heart of the lookup problem is a scalable TCAM implementation which is based on a hash table and presented in [20]. In comparison to a traditional TCAM, it uses less resources and scales linearly in its resource requirements with the number of entries.…”
Section: ) Session Lookup Port and State Table Timers And Event Enmentioning
confidence: 99%
“…One N -bit BV is stored in each RAM, indicating the match condition of the RAM's search key. Such RAM-based lookup mechanism is as efficient as TCAM [10]. …”
Section: B Flow Tablementioning
confidence: 99%
“…However, TCAMs are expensive, power-hungry, and not scalable with respect to clock rate or circuit area [9], [10]. FPGA technologies have become an attractive option for implementing real-time network processing engines [11], [12], [13].…”
Section: Introductionmentioning
confidence: 99%
“…14 The 4-port 1 BgE NetFPGA Xilinx Virtex-II Pro 50 has been selected based on the following requirements: a platform capable of supporting high data rates (near-application-specific integrated circuit (ASIC) performance); 11,15 flexible enough to allow the implementation of a completely new core network forward engine. Due to the NetFPGA platform capabilities, it has been used previously to implement an IP-less forwarding fabric named Bloom-filter based.…”
Section: Keyflow and Openflow Implementationmentioning
confidence: 99%