ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation

Ye, Hanchen; Hao, Cong; Cheng, Jianyi; Jeong, Hyunmin; Huang, Jack; Neuendorffer, Stephen; Chen, Deming

doi:10.1109/hpca53966.2022.00060

Cited by 28 publications

(8 citation statements)

References 37 publications

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“…All other measurements are collected from Vivado synthesis reports. As Vitis HLS operates on C++ representations, we generate such a representation for our test cases by first lowering each DNN layer to the affine dialect and then applying the scalehls-translate tool of the ScaleHLS project [47] to emit C++. Importantly, we do not make any use of scalehls-opt optimization tool (of the same project).…”

Section: Discussionmentioning

confidence: 99%

“…The affine dialect, on the other hand, provides a formalization of semantics that lend themselves to polyhedral compilation techniques [9] that enable loop dependence analysis and loop transformations. Such loop transformations, particularly loop unrolling, are crucial for achieving lowest possible latencies [47] because loop nests directly inform the concurrency and parallelism of the final RTL design.…”

Section: Mlir Mlirmentioning

confidence: 99%

“…Several projects aim to support translation from high-level representations of DNNs to feasible FPGA designs. Typically they rely on commercial HLS tools for the scheduling, binding, and RTL emission phases of the translation, such as in the cases of DaCeML [40], hls4ml [17], and ScaleHLS [47], which all rely on Xilinx's Vitis HLS. Thus, they fail to efficiently (i.e., without incurring the aforementioned runtime costs) produce feasible and low-latency designs.…”

Section: Related Workmentioning

confidence: 99%

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OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

Levental¹,

Khan²,

Chard³

et al. 2023

Preprint

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In many experiment-driven scientific domains, such as high-energy physics, material science, and cosmology, high data rate experiments impose hard constraints on data acquisition systems: collected data must either be indiscriminately stored for post-processing and analysis, thereby necessitating large storage capacity, or accurately filtered in real-time, thereby necessitating low-latency processing. Deep neural networks, effective in other filtering tasks, have not been widely employed in such data acquisition systems, due to design and deployment difficulties. We present an open source, lightweight, compiler framework, without any proprietary dependencies, OpenHLS, based on high-level synthesis techniques, for translating high-level representations of deep neural networks to low-level representations, suitable for deployment to near-sensor devices such as field-programmable gate arrays. We evaluate OpenHLS on various workloads and present a case-study implementation of a deep neural network for Bragg peak detection in the context of high-energy diffraction microscopy. We show OpenHLS is able to produce an implementation of the network with a throughput 4.8 µs/sample, which is approximately a 4× improvement over the existing implementation.

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Section: Discussionmentioning

confidence: 99%

Section: Mlir Mlirmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

Levental¹,

Khan²,

Chard³

et al. 2023

Preprint

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“…[28] is optimized for the on-board Deep Learning Processor Units (DPUs) in Xilinx products rather than FPGAs. On the other hand, recent HLS research works [29,30] have come to support PyTorch in their frameworks as shown in Fig. 5(a).…”

Section: High-level Synthesis Tool For Raster-scan-based Wired-logic ...mentioning

confidence: 99%

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA

LI,

ZHAN,

SUMIKAWA

et al. 2024

IEICE Trans. Electron.

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A 0.13mJ/prediction with 68.6% accuracy wired-logic deep neural network (DNN) processor is developed in a single 16-nm fieldprogrammable gate array (FPGA) chip. Compared with conventional von-Neumann architecture DNN processors, the energy efficiency is greatly improved by eliminating DRAM/BRAM access. A technical challenge for conventional wired-logic processors is the large amount of hardware resources required for implementing large-scale neural networks. To implement a large-scale convolutional neural network (CNN) into a single FPGA chip, two technologies are introduced: (1) a sparse neural network known as a non-linear neural network (NNN), and (2) a newly developed raster-scan wired-logic architecture. Furthermore, a novel high-level synthesis (HLS) technique for wired-logic processor is proposed. The proposed HLS technique enables the automatic generation of two key components: (1) Verilog-hardware description language (HDL) code for a raster-scan-based wired-logic processor and (2) test bench code for conducting equivalence checking. The automated process significantly mitigates the time and effort required for implementation and debugging. Compared with the state-of-the-art FPGA-based processor, 238 times better energy efficiency is achieved with only a slight decrease in accuracy on the CIFAR-100 task. In addition, 7 times better energy efficiency is achieved compared with the state-of-the-art network-optimized application-specific integrated circuit (ASIC).

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“…Open-source (e.g., LegUp [9]) and commercial (e.g., Vitis HLS [10]) tools arose from the efforts of customized high-level compilers for rapid accelerator design. Recent Multi-Level Intermediate Representation (MLIR) [11] efforts aim to build reusable and extensible compiler infrastructure [12] including algorithm-centric Python-based programming and synthesis flow for FPGA [13] and IC synthesis [14].…”

mentioning

confidence: 99%

Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

Ige,

Yang,

Yang

et al. 2023

JLPEA

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The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting.

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ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation

Cited by 28 publications

References 37 publications

OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA

Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

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