Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI

An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management

“…At the circuit level, buffer insertion and gate sizing (physical design process) can be made thermally aware because interconnect and gate delays are strongly dependent on temperature [33]. Besides synthesis, placement, and routing algorithms, power-grid analysis can be made thermally aware to ensure acceptable voltage-drop levels in the presence of significant chip substrate temperature gradients [8,10].…”

“…Increased temperature deteriorates circuit performance by degrading device carrier mobility and increasing interconnect metal resistivity. This, in turn, will impact physical design issues including Power/Ground integrity [8] and placement and routing schemes [9][10][11]. At the system-level, thermal management (packaging and cooling) solutions are also affected by substrate temperature because they have to meet the maximum heatflux requirements at the silicon-package interface [12].…”

“…Relationships between discretized cells are governed by the heat partial differential equations and boundary conditions shown in (7) and (8). Physical thermal parameters, such as thermal conductivity, density, and specific heat of different layers, depend on material properties.…”

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Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip

“…Secondly, higher switching frequency increases ∆I drop. in 65 nm technology if the necessary precautions are not taken [3]. Mitigating power supply noise becomes a grand challenge for the sustainability of future largescale integration development.…”