2014 IEEE 15th International Conference on High Performance Switching and Routing (HPSR) 2014
DOI: 10.1109/hpsr.2014.6900895
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Scaling multi-core network processors without the reordering bottleneck

Abstract: Today, designers of network processors strive to keep the packet reception and transmission orders identical, and therefore avoid any possible out-of-order transmission. However, the development of new features in advanced network processors has resulted in increasingly parallel architectures and increasingly heterogeneous packet processing times, leading to large reordering delays. In this paper, we introduce novel scalable scheduling algorithms for preserving flow order in parallel multi-core network process… Show more

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Cited by 5 publications
(7 citation statements)
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References 27 publications
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“…As mentioned, in our online technical report [13], we further discuss the implementation overhead and prove the correctness of the RP 3 algorithm. Specifically, we estimate the addional control overhead as 40, 60 and 160 bits per packet in Framework 1, 2 and 3, respectively.…”
Section: B Algorithm Descriptionmentioning
confidence: 96%
See 3 more Smart Citations
“…As mentioned, in our online technical report [13], we further discuss the implementation overhead and prove the correctness of the RP 3 algorithm. Specifically, we estimate the addional control overhead as 40, 60 and 160 bits per packet in Framework 1, 2 and 3, respectively.…”
Section: B Algorithm Descriptionmentioning
confidence: 96%
“…The RP 3 algorithm under Framework 2 is quite similar to the described RP 3 algorithm under Framework 1, and therefore we detail it in our online technical report [13].…”
Section: Rpmentioning
confidence: 99%
See 2 more Smart Citations
“…In our model, similarly to [7], upon processing a U -packet for the first time, its properties become known. We therefore refer to such a first processing cycle of a U -packet as a parsing cycle.…”
Section: A System Modelmentioning
confidence: 99%