Scaling, power, and the future of CMOS

Horowitz, Mark; Alon, Elad; Patil, Dinesh; Naffziger, Samuel; Kumar, Rajesh; Bernstein, K.

doi:10.1109/iedm.2005.1609253

Cited by 190 publications

(54 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…A general ternary inverter is an operator (gate) with one input x, and three outputs (denoted by y 0 , y 1 , and y 2 ) such that (2) Therefore, the implementation of ternary inverter requires three inverters, and they are a negative ternary inverter (NTI), a (2) are the outputs [19]. The truth table of the three ternary inverters is shown in Table 3.…”

Section: Ternary Invertermentioning

confidence: 99%

“…The outputs of NTI and PTI correspond to y 0 and y 2 , as given previously in Eq. (2). Figure 17 shows the symbols of NTI, STI, and PTI.…”

Section: Cntfet Based Ternary Gate Designmentioning

confidence: 99%

“…As device physical gate length is reduced to below 25 nm at/beyond 65 nm technology node, various leakage currents and device parameter variationbecome the mostimportant considerations for device optimization. In fact, it can be argued that reduction of gate length below 25 nm may not offer the same advantage as short-gate devices had provided historically in terms of power and performance at the system level [2]. The major detractors are: the lack of a thin equivalent gate oxide (with low leakage current) for effective short channel effect control, the increasing contribution of the fringing parasitic capacitance to the total gate capacitance, and the rising contribution of the source/drain resistance to the total device on-resistance [3].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Kim¹

2011

Transactions on Electrical and Electronic Materials

View full text Add to dashboard Cite

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

show abstract

Section: Ternary Invertermentioning

confidence: 99%

“…The outputs of NTI and PTI correspond to y 0 and y 2 , as given previously in Eq. (2). Figure 17 shows the symbols of NTI, STI, and PTI.…”

Section: Cntfet Based Ternary Gate Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Kim¹

2011

Transactions on Electrical and Electronic Materials

View full text Add to dashboard Cite

show abstract

“…The early concept of scaling for MOS transistors was to reduce all of the dimensions by the same amount α [2,3]. Device and technology developments in recent years, however, have shown that scaling is more and more limited by material properties and power dissipation [4][5][6]. Especially improvements of the short-channel behaviour, current drive and switching behaviour are main issues to obtain the projected performance increase [5].…”

Section: Introductionmentioning

confidence: 98%

Wafer bonding in silicon electronics

Reiche

2009

Phys. Status Solidi (c)

View full text Add to dashboard Cite

Semiconductor wafer bonding offers a new degree of freedom in the design of material combinations without the common restrictions of the structure of the materials bonded. It is already an established method for the industrial production of advanced substrates (SOI) applied as basic material in high‐performance device fabrication. SOI, i.e. a thin device layer on an insulator, is a promising concept for further device developments. The advantages of SOI can be combined with mobility enhancing materials such as strained silicon (SSOI) or germanium on insulator (GOI). The bonding process is not limited to a certain wafer diameter and is applicable to different material combinations which are important to integrate different functions on a chip (system on a chip, SoC). (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

show abstract

“…In additio process-induced variations is severe in t especially at low temperatures. This inc variability often limits the effectiveness of V performance constraints [3][4][5][6]. The delay distr regime and cold temperature is inherently no large skewness ( Figure 1).…”

Section: Introductionmentioning

confidence: 99%

Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications

Balasubramanian

Pimparkar

Kushare

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

Ultra low power (ULP) applications use (Vdd) scaling as an effective way of r However, as Vdd is scaled near the thresho increased variability limits the minimum Vd can be realized. This paper outlines a framework to capture the total delay variatio circuits and describes its applicability for nea variability analysis. The low-voltage variab has been validated against 14nm-FinFET rin measurements.

show abstract

Scaling, power, and the future of CMOS

Cited by 190 publications

References 27 publications

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Wafer bonding in silicon electronics

Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications

Contact Info

Product

Resources

About