Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

Miyaji, Kagami; Hung, Chinglin; Takeuchi, Ken

doi:10.7567/jjap.51.04dd12

Cited by 7 publications

(3 citation statements)

References 9 publications

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“…Therefore, with newly proposed scheme not only 1 layered NAND flash memory but also large part of HDD [4] can be replaced. At present 1 layered NAND flash memory reaches to the limitation of scaling [5]. With the newly proposed scheme there is a possibility to realize low cost non-volatile semiconductor memory with the smaller value of design rule compared with 1 layered NAND flash memory.…”

Section: Introductionmentioning

confidence: 99%

Design method of stacked type NAND MRAM with ultra low bit cost

Tamai¹,

Watanabe

2013

ces

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In this paper design method for stacked type NAND MRAM which can achieve ultra low bit cost compared with that of previously proposed stacked type NAND MRAM and performance competitive to 1 layered NAND flash memory has been newly proposed. For realizing the ultra low bit cost it is assumed that the process technology with which minimum number of process steps can be achieved. With the newly proposed scheme low bit cost as small as 1/100 of that of 1 layered NAND flash memory, (1/10 of that of previously proposed stacked type NAND MRAM) can be realized using the same design rule. Therefore, with newly proposed scheme not only 1 layered NAND flash memory but also high end and middle range HDD can be replaced.

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Section: Introductionmentioning

confidence: 99%

Design method of stacked type NAND MRAM with ultra low bit cost

Tamai¹,

Watanabe

2013

ces

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“…Furthermore, the shrinking induced larger S-factor severely reduces the on/off ration of the NAND flash, which is a substantial parameter in the multi-level cell (MLC)/triple-level cell (TLC) bit technology [22].…”

Section: Scaling Challenge Of the Conventional Nand Flash Memorymentioning

confidence: 99%

Characterization of nanoscale conducting filament in high-k oxides by scanning tunneling microscopy and conductive atomic force microscopy

Zhou¹

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By virtue of its simple structure, high operating speed and scalability, the resistive memory or RRAM is deemed a promising alternative to the charge-based memory, which is now facing severe scaling challenges. Of particular interest is the HfO 2 RRAM due to its immediate compatibility with mainstream integrated-circuit technology. A major problem is, however, the relatively high switching current.Currents on the order of 10 -3 A are typically observed in large-area cells (~10 -8 cm 2 ).In a recent work, a substantial reduction of the switching current to ~10 -5 A was achieved by scaling the cell area down to 100 nm 2 .Since one of the main strengths of RRAM is scalability, a further reduction of the switching current is deemed necessary in order to make ultra-high density memory application viable. At present, it is unclear to what extent could the switching current be reduced with cell area scaling. To address this question, resistance switching in HfO 2 is examined using a conductive atomic force microscope (C-AFM) and scanning tunneling microscope (STM) in this thesis. The excellent spatial resolution of C-AFM and STM enables the electrical properties of a thin dielectric to be probed over an extremely localized region. Through the C-AFM/STM technique, in this thesis, we examined resistance switching in a 4-nm thick HfO 2 , within a region of ~2 nm in diameter and achieved an ultra-low current switching capability. Furthermore, the unique abrupt reset behavior is observed in nanoscale RRAM with nanometer-level conducting filament (CF), on the contrary, the gradual current reduction trend is typically observed during the reset process in relatively large area

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“…However, further scaling is limited by issues of electromagnetic interference reducing memory integrity, shortchannel effects, drain-induced barrier lowering, weaker ON/OFF ratio etc. reducing its scaling potential and ability to take clear advantage of lower node scaling [14][15][16]. This has led to efforts in other directions, such as the architecture through the use of 3Dstacked NAND [17][18][19].…”

Section: 7mentioning

confidence: 99%

Functionalization of transparent oxide resistive random-access memories for visible light photosensitivity

Kalaga¹

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vi ACKNOWLEDGEMENT Sri Gurubhyo Namah| Sri Matre Namah|| My salutations to the Guru and Mother who have given me the strength, opportunity, fortitude and blessings to undertake a PhD. My sincere gratitude and thanks goes to my supervisor, Prof. Ang Diing Shenp from Nanyang Technological University (NTU), for offering me the opportunity to pursue a PhD degree under his supervision on the exciting topic that is the subject of this thesis. His sound technical guidance, constructive discussion and creative insights into semiconductor research have been the mainstay of my training in advanced research. His constant guidance and commitment to enriching the field of science have inspired my own approach to the world of scientific and technical research. I offer my sincere thanks to him for providing me with the opportunity to have worked with him.I also take this opportunity to thank Nanyang Technological University for the opportunity to pursue a PhD at a world-class institution along with the excellent research facilities and infrastructure available here, as well as for the various seminars that were organized which helped expand my knowledge of the research space. I would also like to thank Prof. Lew Wen Siang and Prof. Wang Hong for their assistance as members of my thesis advisory committee. My thanks go to the various technical and administrative staff I have interacted with for the equipment training, upkeep of facilities as well as quick redressal of issues that might have otherwise hampered my research pursuits.

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Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

Cited by 7 publications

References 9 publications

Design method of stacked type NAND MRAM with ultra low bit cost

Design method of stacked type NAND MRAM with ultra low bit cost

Characterization of nanoscale conducting filament in high-k oxides by scanning tunneling microscopy and conductive atomic force microscopy

Functionalization of transparent oxide resistive random-access memories for visible light photosensitivity

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