Scan based speed-path debug for a microprocessor

Zeng, Jing; Guo, Ruifeng; Cheng, Wu-Tung; Mateja, Michael; Wang, Jing; Tsai, Kun-Han; Amstutz, Ken

doi:10.1109/etsym.2010.5512756

Cited by 16 publications

(2 citation statements)

References 14 publications

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“…State-of-the-art test automation tools can perform accurate and high-resolution diagnosis at chip level [21]. However, the test environment is more challenging and complex at board level.…”

Section: Problem Statement and Paper Contributionsmentioning

confidence: 99%

Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees

Zhang

Chakrabarty

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Board-level functional fault diagnosis is needed for high-volume production to improve product yield. However, to ensure diagnosis accuracy and effective board repair, a large number of syndromes must be used. Therefore, the diagnosis cost can be prohibitively high due to the increase in diagnosis time and the complexity of test execution and analysis. We propose an adaptive diagnosis method based on incremental decision trees. Faulty components are classified according to the discriminative ability of the syndromes in decision-tree (DT) training. The diagnosis procedure is constructed as a binary tree, with the most discriminative syndrome as the root and final repair suggestions are available as the leaf nodes of the tree. The syndrome to be used in the next step is determined based on the observation of syndromes thus far in the diagnosis procedure. The number of syndromes required for diagnosis can be significantly reduced compared to the total number of syndromes used for system training. Moreover, online learning is facilitated in the proposed diagnosis system using an incremental version of DTs, so as to bridge the knowledge obtained at test-design stage with the knowledge gained during volume production. The diagnosis system can thus adapt to occurrences of new error scenarios on-the-fly. Diagnosis results for three complex boards from industry, currently in volume production, highlight the effectiveness of the proposed approach.

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“…State-of-the-art test automation tools can perform accurate and high-resolution diagnosis at chip level [21]. However, the test environment is more challenging and complex at board level.…”

Section: Problem Statement and Paper Contributionsmentioning

confidence: 99%

Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees

Zhang

Chakrabarty

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Delays of a small set of representative speedpaths are measured in [5] to predict failing speedpaths using a statistical learning-based approach. The work in [6] uses at-speed scan test patterns to debug failing speedpaths. The real-time visibility of speedpaths is provided by using trace buffers in [7] to diagnose speedpaths.…”

Section: Introductionmentioning

confidence: 99%

Efficient automated speedpath debugging

Dehbashi

Fey

2013

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Speedpath diagnosis is one of the major challenges in designing high-performance Very-Large-Scale Integrated (VLSI) circuits due to timing variations caused by process variations and environmental effects. In this paper, an efficient approach to automate speedpath debugging is presented. The approach relies on converting the timing behavior of a circuit and its corresponding timing variations into functional domain. Afterwards, a SAT-based debug engine is utilized to extract potential failing speedpaths. The experimental results on ISCAS'85 and ISCAS'89 benchmark suites show that our approach achieves a 63% decrease in the size of model resulting in 54% decrease in the debugging time compared to previous work while having a high diagnosis accuracy. I. INTRODUCTIONDebugging of speedpaths is a major concern in developing high performance VLSI circuits. At the post-silicon stage, a speedpath may violate timing constraints due to timing variations induced by process variations and other environmental effects. After detecting a speed failure due to frequency constraints [1], the debugging starts to identify failing speedpaths. But this process requires a large effort which consumes a significant portion of the IC development cycle. In this case, automated approaches to debug speedpaths can reduce the development time of IC products.The work in [2] utilizes integer linear programming to diagnose segments of failing speedpaths caused by process variations. On-chip delay sensors are used in [3] to improve timing prediction in order to isolate failing speedpaths. Failure logs are processed in [4] at various slower-than-nominal clock frequencies to enhance the diagnosis accuracy. Delays of a small set of representative speedpaths are measured in [5] to predict failing speedpaths using a statistical learning-based approach. The work in [6] uses at-speed scan test patterns to debug failing speedpaths. The real-time visibility of speedpaths is provided by using trace buffers in [7] to diagnose speedpaths. The work in [8] uses fault dictionary as well as forward propagation and backward implication techniques to diagnose stuck-at, stuck-open and delay faults. Diagnosis based on fault dictionaries is computationally efficient. But this requires a tight link between test generation and observation of erroneous behavior. Moreover, typically no model for variation is underlying dictionary based diagnosis.The work in [9] investigates the relationship between the quality of the test vectors for post-silicon validation and the accuracy of yield-performance predictions. Functional tests and implications are utilized in [10] to automate speedpath debugging. Using only functional implications without incorporating timing information limits the diagnosis accuracy. The work in [11] presents a model based on Boolean satisfiability to automate debugging. But no timing information is included in the model. A timing analysis tool is proposed in [12] that integrates a pattern-dependent delay model into its analysis. An approach to automate the...

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Automated Debugging for Logic Bugs

Dehbashi

Fey

2014

Debug Automation From Pre-Silicon to Post-Silicon

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Scan based speed-path debug for a microprocessor

Cited by 16 publications

References 14 publications

Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees

Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees

Efficient automated speedpath debugging

Automated Debugging for Logic Bugs

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