Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Abstract

A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC.

A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic

“…The shortest execution times T E , along with the smallest resource usage, were reported by Sreenivasappa and Udaykumar [37]. Similar results were obtained by Dhanabalan et al [25]. The actual calculations are carried out with combinatorial structures capable of generating the result in one clock cycle.…”

“…Although the implementation of the PID algorithm in FPGA devices is described in many research papers, only some of them deal directly with the circuit microarchitecture, i.e., how the digital circuit is made up of its hardware components. These include the studies reported in [21,25,32,36,37,[39][40][41][42][43]. The same functionality can be implemented in a digital circuit following various structural schemes.…”

“…The implementation of arithmetic functions operating on fixedpoint numbers is much simpler and cheaper in terms of logic resources consumed. In most of the aforementioned works, fixed-point representations are used, with the length of the binary number ranging from 8 [25,36,37] to 32 bits [13].…”

“…If implemented in an MCU or DSP, more control loops slow down the controller operation due to the sequential execution of program instructions, which is inherent for these devices. This does not concern implementations in an FPGA, as the same controller circuitry can be easily replicated, and operate concurrently [25]. • The possibility of combining a PID regulator with other functions and integrating them conveniently in a single device.…”

Usage of fractional order $${\textrm{PI}}^\lambda {\textrm{D}}^\mu$$ controller as AQM algorithm

“…In this paper, we present the implementation of controller using dedicated Field Programmable Gate Arrays (FPGA) design to calculate the response values of the controller. The FPGA-based designs to calculate the response of PID controllers are present in various fields like motion control systems 24 , respiratory systems 25 or industrial PLC controllers 26 . Among currently existing solutions, there are also already taken attempts to implement a fractional-order controller with FPGA 27 .…”