SCCN: A Time-Effective Hierarchical Interconnection Network for Network-On-Chip

Ali, Mohammed N. M.; Rahman, M.M. Hafizur; Nor, Rizal Bin Mohd.; Behera, Dhiren Kumar; Sembok, Tengku Mohd Tengku; Miura, Yasuyuki; Inoguchi, Yasushi

doi:10.1007/s11036-019-01262-2

Cited by 12 publications

(11 citation statements)

References 14 publications

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“…The total number of the used wires to connect each node to the other nodes in the interconnection network known as the wiring complexity (Ali et al, 2016b). It has a crucial effect on the network cost and complexity.…”

Section: Wiring Complexitymentioning

confidence: 99%

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The connectivity and the static-cost-effective analysis of a shifted completely connected network

et al. 2019

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At the current time, finding an alternative computing device with extreme computation power is the main concern of the research community. Therefore, building a computer device able to execute extremely difficult calculations in a short period of time is required. Presently, the massively parallel computer (MPC) systems are considered the highest computing devices, and the existence of these systems is important to execute many operations in many sectors such as engineering and science. These devices are built based on an internal network called interconnection network has a

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Section: Wiring Complexitymentioning

confidence: 99%

“…In order to improve the performance and to expand the interconnection network size, many new designs of network topologies have been proposed (Ali et al, 2016b;Rahman et al, 2009a;Asaduzzaman et al, 2013). These networks divided into conventional networks and hierarchical networks.…”

Section: Introductionmentioning

confidence: 99%

The connectivity and the static-cost-effective analysis of a shifted completely connected network

et al. 2019

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“…Network-on-chip (NoC) offers a flexible and scalable solution to satisfy the communication bandwidth for the many-core system-on-chip (SoC) [1][2][3][4][5]. Suffering from high power cost, long network latency, and low network throughput [2,6,7], the overall performance of existing NoC systems is undesirable.…”

Section: Introductionmentioning

confidence: 99%

ParRouting: An Efficient Area Partition-Based Congestion-Aware Routing Algorithm for NoCs

Fang

Zhang

2020

Micromachines

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Routing algorithms is a key factor that determines the performance of NoC (Networks-on-Chip) systems. Regional congestion awareness routing algorithms have shown great potential in improving the performance of NoC. However, it incurs a significant queuing latency when practitioners use existing regional congestion awareness routing algorithms to make routing decisions, thus degrading the performance of NoC. In this paper, we propose an efficient area partition-based congestion-aware routing algorithm, ParRouting, which aims at increasing the throughput and reducing the latency for NoC systems. First, ParRouting partitions the network into two areas (i.e., edge area and central area.) based on node priorities. Then, for the edge area, ParRouting selects the output node based on different priorities for higher throughput; for the central area, ParRouting selects the node in the low congestion direction as the output node for lower queuing latency. Our experimental results indicate that ParRouting achieves a 53.4% reduction in packet average latency over SPLASH -2 ocean application and improves the saturated throughput by up to 38.81% over a synthetic traffic pattern for an NoC system, compared to existing routing algorithms.

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“…The early structures of the interconnection network topologies showed poor performance with the increase of the network size [7]. Therefore, to solve this problem, hierarchical interconnection networks (HINs) were proposed to be an alternative solution to replace the conventional networks in building MPC systems [8]. These networks proved their capability in expanding the number of computing nodes inside the system to millions of nodes.…”

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confidence: 99%

The Static Performance Effect of Hybrid- Hierarchical Interconnection by Shifted Completely Connected Network

et al. 2021

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Massively parallel computer (MPC) systems execute many operations based on internal networks called interconnection networks. The performance of these networks is affected by their topologies.There are many topologies of interconnection networks for MPC systems, unfortunately, they faced many drawbacks. Expanding the size of the network degrades the performance of these topologies. That is why this current paper presents a hybrid-hierarchical interconnection network (HIN) topology by Shifted Completely Connected Network (SCCN) to circumvent the drawbacks of the existing topologies. An experimental evaluation involving the design and development of a hierarchical network was carried out. A two-dimensional higher level networks has been produced and its static network performance parameters evaluated through simulators. The finding of the simulations has shown some good performances compared to many previous designed networks. SCCN is better than all conventional networks in terms of diameter, cost and average distance.

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SCCN: A Time-Effective Hierarchical Interconnection Network for Network-On-Chip

Cited by 12 publications

References 14 publications

The connectivity and the static-cost-effective analysis of a shifted completely connected network

The connectivity and the static-cost-effective analysis of a shifted completely connected network

ParRouting: An Efficient Area Partition-Based Congestion-Aware Routing Algorithm for NoCs

The Static Performance Effect of Hybrid- Hierarchical Interconnection by Shifted Completely Connected Network

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