Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling

Abstract

With the rapid progress in semiconductor technology and the shrinking of device geometries, the resulting processors are increasingly becoming prone to effects like aging and soft errors. As a processor ages, its electrical characteristics degrade, i.e., the switching times of its transistors increase. Hence, the processor cannot continue error-free operation at the same clock frequency and/or voltage for which it was originally designed. In order to mitigate such effects, recent research proposes to equip processors with special circuitry that automatically adapts its clock frequency in response to changes in its circuit-level timing properties (arising from changes in its electrical characteristics). From the point of view of tasks running on these processors, such autonomic frequency scaling (AFS) processors become slower as they gradually age. This leads to additional execution delay for tasks, which needs to be analyzed carefully, particularly in the context of hard realtime or safety-critical systems. Hence, for real-time systems based on AFS processors, the associated schedulability analysis should be aging-aware which is a relatively unexplored topic so far. In this paper we propose a schedulability analysis framework that accounts such aging-induced degradation and changes in timing properties of the processor, when designing hard real-time systems. In particular, we address the schedulability and task mapping problem by taking a lifetime constraint of the system into account. In other words, the system should be designed to be fully operational (i.e., meet all deadlines) till a given minimum period of time (i.e., its lifetime). The proposed framework is based on an aging model of the processor which we discuss in detail. In addition to studying the effects of aging on the schedulability of real-time tasks, we also discuss its impact on task mapping and resource dimensioning.

Reliable CPS Design for Unreliable Hardware Platforms

“…Other than increasing the supply voltage, decreasing the operating frequency actually lowers the power consumption. However, the processor becomes slower, which results in degraded control performance [4] and schedulability issues [12]. Nevertheless, dynamic operating frequency adjustments are a promising approach due to not negatively impacting the overall energy consumption while maintaining high usage of resources.…”

Automotive Cyber–Physical Systems: A Tutorial Introduction

“…As a processor ages, the switching time of its transistors increases, resulting in longer path delays [34]. A common way to deal with such effects is to reduce the processor's operating frequency to ensure that the signal transmission in any path can be completed within one clock cycle [35]. Obviously, the WCET of control tasks gets longer with a lower operating frequency.…”

Hayat

“…For each candidate cores C cand. ∈ C (line 5) this thread can use (i.e., fulfills the speed requirements), it evaluates the possible outcomes in terms of temperature and health (line [7][8][9][10][11][12][13][14][15][16][17][18][19].…”

“…Afterwards, the chip's health profile is estimated using the lookup process discussed in Section IV-B (line 15). Average values for health (Havg,next) and temperature (Tavg,next) are determined and pushed as a candidate solution to our list S (line [17][18][19]. Finally, the algorithm sorts S according to a weighting function (will be shortly explained below) and assign the currently processed thread the best candidate (line [22][23].…”

“…Chip-level performance degradation can no longer be addressed by simply employing design-time guardbanding [12,16]. A class of related work targets aging-aware application scheduling [17], but such techniques do not account for temperature and process variations. The FaceLift approach in [11] reduces aging through chip-wide changes to V dd and performs workload-aware task scheduling considering process variations.…”