Scheduler-based DRAM energy management

Delaluz, V.; Sivasubramaniam, Anand; Kandemir, Mahmut; Narayanan, Vijaykrishnan; Irwin, M.J.

doi:10.1145/513918.514095

Cited by 64 publications

(26 citation statements)

References 16 publications

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“…Some techniques for incorporating power optimization decisions with context switching have also been discussed. Delaluz et al [11] keeps track of memory banks used for each application and selectively turn them on or off with each context switch to manage energy consumption of DRAM per application. Huang et.…”

Section: Related Workmentioning

confidence: 99%

Towards Practical Page Placement for a Green Memory Manager

Panwar

Gopinath

2015

2015 IEEE 22nd International Conference on High Performance Computing (HiPC)

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Increased performance demand of modern applications has resulted in large memory modules and higher performance processors in computing systems. Power consumption becomes an important aspect when these resources go underutilized in a running system; e.g. during idle periods or lighter workloads. CPUs have come a long way in optimizing away the unnecessary power consumption in both hardware and software for such scenarios through solutions like Dynamic Voltage/Frequency Scaling. However, support for memory power optimization is still missing in modern operating systems despite hardware support being available for many years in the form of multiple power states and techniques like Partial Array SelfRefresh.In this work, we explore the behavior of Linux memory manager and report that even at 10% of memory utilization, there are references to all physical memory banks in a long running system due to random page allocation and ignorance of memory bank boundaries. These references can be consolidated to a subset of memory banks by using page migration techniques. Unfortunately, migration of large contiguous blocks is often restricted due to the presence of unmovable pages primarily owned by kernel.We provide some techniques for utilizing the hardware facilitated Partial Array Self-Refresh by introducing bank awareness in the existing buddy allocation framework of Linux memory manager as well as for improving the page migration support of large contiguous blocks. Through a set of simple changes in Linux VM, we have been able to reduce the number of referenced memory banks significantly. Memory-hotplug framework, which relies on page migration of large contiguous blocks, also shows significant improvement in terms of number of removable memory sections. Benchmark results show no performance degradation in the modified kernel which makes the proposed solution desirable.

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Section: Related Workmentioning

confidence: 99%

Towards Practical Page Placement for a Green Memory Manager

Panwar

Gopinath

2015

2015 IEEE 22nd International Conference on High Performance Computing (HiPC)

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“…The modern physical memory DRAM technology has matured to provide up to six low power modes [18] . [19][20][21] propose several methods and algorithms to adjust the DRAM power mode during the execution of programs in real time.…”

Section: Related Workmentioning

confidence: 99%

Energy Efficiency of a Multi-Core Processor by Tag Reduction

Zheng

Dong

Ota

et al. 2011

J. Comput. Sci. Technol.

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We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor.

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“…The modern physical memory DRAM technology has matured to provide up to six low power modes [8]. [9] [10] [11] propose several methods and algorithms to adjust the DRAM power mode during the execution of programs in real time. Also, the energy reduction is available in cache system, [12] [13] focuses on a low-cost set-associative cache organization.…”

Section: Introductionmentioning

confidence: 99%

An Improved Approach to Tag Reduction on Low Power CMP with Trade-Off of Energy and Performance

Zheng

Dong

Jin

et al. 2009

2009 Fourth International Conference on Frontier of Computer Science and Technology

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Energy consumption and performance are always major considerations in microprocessor optimization. However, mostly, saving energy causes performance decrement. Based on the previous energy saving research on tag reduction for low power Chip Multiprocessor (CMP), we proposed an improved approach to balance energy and performance by introducing an affiliation degree. To our best knowledge, this is the first work that analyzes the energy and performance of tag reduction on CMP. We also formulate the trade-off of energy and performance to an equivalent problem which is to find out an appropriate affiliation degree to get the benefit with tradeoff of energy and performance most. In the experiment, we apply our approach to a 16-core CMP with help of simulation. The experiment results show that when affiliation degree is 12, the energy saving and performance cost of tag reduction on CMP can be balanced best.

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Scheduler-based DRAM energy management

Cited by 64 publications

References 16 publications

Towards Practical Page Placement for a Green Memory Manager

Towards Practical Page Placement for a Green Memory Manager

Energy Efficiency of a Multi-Core Processor by Tag Reduction

An Improved Approach to Tag Reduction on Low Power CMP with Trade-Off of Energy and Performance

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