Scheduling Algorithms with Bus Bandwidth Considerations for SMPs

Antonopoulos, Christos D.; Nikolopoulos, Dimitrios S.; Papatheodorou, Theodore S.

doi:10.1002/0471732710.ch16

Cited by 10 publications

(22 citation statements)

References 9 publications

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“…It may be possible to acquire such information by automated experimentation [22,23] or by correlating profiling statistics with application properties [5,10,25,30]. The most straight forward approach, however, is to simply ask the user.…”

Section: Symbiotic Space-sharing In Prac-ticementioning

confidence: 99%

User-guided symbiotic space-sharing of real workloads

Weinberg

Snavely

2006

Proceedings of the 20th Annual International Conference on Supercomputing

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Symbiotic space-sharing is a technique that can improve system throughput by executing parallel applications in combinations and configurations that alleviate pressure on shared resources. We have shown prototype schedulers that leverage such techniques to improve throughput by 20% over conventional space-sharing schedulers when resource bottlenecks are known. Such evaluations have utilized benchmark workloads and proposed that schedulers be informed of resource bottlenecks by users at job submission time; in this work, we investigate the accuracy with which users can actually identify resource bottlenecks in real applications and the implications of these predictions for symbiotic space-sharing of production workloads. Using a large HPC platform, a representative application workload, and a sampling of expert users, we show that user inputs are of value and that for our chosen workload, userguided symbiotic scheduling can improve throughput over conventional space-sharing by 15-22%.

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Section: Symbiotic Space-sharing In Prac-ticementioning

confidence: 99%

User-guided symbiotic space-sharing of real workloads

Weinberg

Snavely

2006

Proceedings of the 20th Annual International Conference on Supercomputing

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“…Even today's simplest parallel machines, such as SMTs or small SMPs, already have diculties with many applications and workload mixes. For example, processes that contend for the same resources (e.g., the memory bus) can experience an overall slowdown on a hyperthreaded system, rather than speedups resulting from parallelism and latency hiding [2,4,20].…”

Section: Overviewmentioning

confidence: 99%

“…Commodity schedulers are challenged at all levels of parallel execution, from the thread [4,35], through the SMP [2,12], the cluster [10,15], all the way to supercomputers [23]. In particular, parallel programs suer tremendously from lack of coscheduling 3 [10,23].…”

Section: Overviewmentioning

confidence: 99%

“…Note that memory hierarchy eects, I/O subsystems, and factors other than scheduling that can aect performance are excluded from this experiment. We predict that with parallel computers, memory bandwidth will become an even more critical resource than it is today, and should be managed by the scheduler [2,4]. Figure 1 shows the results obtained on a four-way HP ES40 SMP with 833MHz Alpha processors, comparing the Linux default scheduler to gang scheduling.…”

Section: Coscheduling Examplementioning

confidence: 99%

“…But unlike classical parallel computers, the presence of various classes of applications in a single workload mixincluding interactive and single-threaded applicationsposes a signicant additional challenge on top of the specic application requirements. Ignoring these scheduling considerations can lead to poor application performance because of lack of synchronization, as well as poor system-wide performance because of contention for resources [2,10,23,35]. These factors paint a bleak picture for future OS performance unless they are accounted for in commodity multiprocessor schedulers.…”

Section: Generalizing the Challengesmentioning

confidence: 99%

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Process Scheduling for the Parallel Desktop

Frachtenberg

8th International Symposium on Parallel Architectures,Algorithms and Networks (ISPAN'05)

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Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power management, and most importantly, chip parallelism. Similarly, workloads are growing more concurrent and diverse. With this new complexity in hardware and software, process scheduling in the operating system (OS) becomes more challenging. Nevertheless, most commodity OS schedulers are based on design principles that are 30 years old. This disparity may soon lead to signicant performance degradation. Most signicantly, parallel architectures such as multicore chips require more than scalable OSs: parallel programs require parallelaware scheduling.This paper posits that imminent changes in hardware and software warrant reevaluating the scheduler's policies in the commodity OS. We discuss and demonstrate the main issues that the emerging parallel desktops are raising for the OS scheduler. We propose that a new approach to scheduling is required, applying and generalizing lessons from different domain-specic scheduling algorithms, and in particular, parallel job scheduling. Future architectures can also assist the OS by providing better information on process scheduling requirements. OverviewCommodity computers and the way we use them changed qualitatively in the last 30 years. The OS, as the intermediary between hardware and software, is required to adapt to the changes in hardware, and the software that uses it. Indeed, many aspects of commodity OSs, such as networking and storage have changed concomitantly. Yet the scheduling policies that lie at the core of the OS remained virtually unchanged during this time [8,23], and are in dire need of modernization. Several important trends in commodity architectures warrant this change, such as increased chip parallelism and heterogeneity, the emergence of power management as a limiting factor in desktop processors, and more complex memory hierarchies. Applications and workloads are also evolving to meet consumer demands and hardware capabilities, each application with its own scheduling requirements.In this paper, we argue that the conuence of parallelism and diverse workloads on the commodity computer warrants revisiting the scheduler's policies. Three postulates support this thesis: commodity hardware is becoming increasingly parallel, the software running on it will follow suit, and the OS will need to support these trends, particularly in terms of scheduling. The main goal of this paper, in Sections 2-4, is to establish these premises and present the case and design goals for scheduler modernization. Next, Section 5 suggests some principles for the development of novel scheduling policies. Finally, we conclude in Section 6.2 Hardware Trends: The Move to ConcurrencyThe phenomenal growth of microprocessor performance has fueled a similarly explosive growth in commodity hardware and applications for more than two decades. However, the growth in single-processor performance is now showing signs of sl...

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Realistic Workload Scheduling Policies for Taming the Memory Bandwidth Bottleneck of SMPs

Antonopoulos

Nikolopoulos

Papatheodorou

2004

Lecture Notes in Computer Science

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In this paper we reformulate the thread scheduling problem on multiprogrammed SMPs. Scheduling algorithms usually attempt to maximize performance of memory intensive applications by optimally exploiting the cache hierarchy. We present experimental results indicating that-contrary to the common belief-the extent of performance loss of memory-intensive, multiprogrammed workloads is disproportionate to the deterioration of cache performance caused by interference between threads. In previous work [1] we found that memory bandwidth saturation is often the actual bottleneck that determines the performance of multiprogrammed workloads. Therefore, we present and evaluate two realistic scheduling policies which treat memory bandwidth as a first-class resource. Their design methodology is general enough and can be applied to introduce bus bandwidth-awareness to conventional scheduling policies. Experimental results substantiate the advantages of our approach.

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Scheduling Algorithms with Bus Bandwidth Considerations for SMPs

Abstract: The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However

Cited by 10 publications

References 9 publications

User-guided symbiotic space-sharing of real workloads

User-guided symbiotic space-sharing of real workloads

Process Scheduling for the Parallel Desktop

Realistic Workload Scheduling Policies for Taming the Memory Bandwidth Bottleneck of SMPs

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