Scheduling and binding algorithms for high-level synthesis

Paulin, Pierre; Knight, J.P.

doi:10.1145/74382.74383

Cited by 116 publications

(41 citation statements)

References 15 publications

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“…Although scheduling and binding in high-level synthesis is a well-studied problem [15][16][17], many of those studies do not consider fault tolerance or error-correction percentage. More recent works have treated reliability as a primary concern in the high-level synthesis process but focus on different reliability goals in ASIC designs.…”

Section: Related Workmentioning

confidence: 99%

“…We provide an informal proof that this problem is NP-hard as follows. If we remove both error constraints from the problem definition, the problem is equivalent to minimum-latency and resourceconstrained scheduling followed by binding, which are both NP-hard problems [15]. The correctable and detectable error constraints only make the problem harder by expanding the solution space with replicated versions of the input.…”

Section: International Journal Of Reconfigurable Computingmentioning

confidence: 99%

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A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.

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Section: Related Workmentioning

confidence: 99%

Section: International Journal Of Reconfigurable Computingmentioning

confidence: 99%

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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“…In previous work [24]- [28], the number of interconnects or multiplexers was used to estimate interconnect cost. The performance and power impacts of interconnect and interconnect buffers are now first-order timing and power considerations in VLSI design [29].…”

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confidence: 99%

Unified Incremental Physical-Level and High-Level Synthesis

Wang

Dick

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level designautomation tools that consider the increasingly important impact of physical features, such as interconnect, on integrated circuit area, performance, and power consumption. Using physical information to guide decisions in the behavioral-level stage of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level-synthesis system. This system integrates high-level and physical-design algorithms to concurrently improve a design's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefits of efficiency, stability, and better quality of results. The average CPU time speedup resulting from unifying incremental physical-level and high-level synthesis is 24.72× and area improvement is 13.76%. The low power consumption of a state-of-the-art low-power interconnect-aware high-levelsynthesis algorithm is maintained. The benefits of concurrent behavioral-level and physical-design optimization increased for larger problem instances.Index Terms-Behavioral synthesis, floorplanning, low power design.

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“…Furthermore, the generated design can be tested easily due to the reduced number of hardware modules. The availability of highdensity and high-speed multiport memories motivates the use of multiport memories in datapath synthesis.Most of the previous approaches allocate variables either to isolated registers or to register files [2][3][4][5]. However, they do not fully utilize the advantages of multiport memories for variable mapping.…”

mentioning

confidence: 99%

“…Most of the previous approaches allocate variables either to isolated registers or to register files [2][3][4][5]. However, they do not fully utilize the advantages of multiport memories for variable mapping.…”

mentioning

confidence: 99%

A scheduling algorithm for multiport memory minimization in datapath synthesis

Lee¹,

Hwang²

1995

Proceedings of the 1995 Conference on Asia Pacific Design Automation (CD-ROM) - ASP-DAC '95

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-In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps , and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. When compared with previous approaches for several benchmarks available from the literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.hence require less chip area, as compared to random logic. Furthermore, the generated design can be tested easily due to the reduced number of hardware modules. The availability of highdensity and high-speed multiport memories motivates the use of multiport memories in datapath synthesis.Most of the previous approaches allocate variables either to isolated registers or to register files [2][3][4][5]. However, they do not fully utilize the advantages of multiport memories for variable mapping. A handful of systems reported the use of multiport memories for datapath designs. Balakrishnan et al. [6] have reported a technique to minimize the number of memory modules. Grouping a maximal number of registers into a cluster, their algorithm assigns a cluster of registers to a multiport memory at a time. The left-over registers are either allocated to isolated registers or grouped into multiport memories by repeatedly applying the same procedure. The algorithm often leads to nonoptimal register allocations in the number of memory modules and interconnection cost. Wilson et. al. [7] presented a heuristic algorithm in which registers are allocated to available multiport memories one-by-one. Due to the local nature of greedy search, the algorithm does not guarantee an optimal solution in the number of memory modules and the number of registers in each memory module. Ahmad et al.[8] formulated the 0-1 integer linear programming (ILP) to generate the minimum number of multiport memory modules, and tried to reduce the number of registers in each memory module. However, by not considering the connections between multiport memory modules and FUs, the algorithm incurs larger inter-connection cost in the final implementation of datapaths. Kim et al.[9] also used the 0-1 ILP to group variables into multiport memory modules, but they did not try to minimize the number of registers in each memory module. Q. INTRODUCTIONDue to the advance of VLSI circuit fabrication and design techniques, it has been become feasible to realize a large-scale system in a single chip. For the productivity enhancement of design engineers, researchers in the CAD community have been attempting to automa...

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Scheduling and binding algorithms for high-level synthesis

Cited by 116 publications

References 15 publications

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Unified Incremental Physical-Level and High-Level Synthesis

A scheduling algorithm for multiport memory minimization in datapath synthesis

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