Scheduling lecturer system based on FPGA

Mohammed, Zaid Ghanim; Hamdoon, Abdullah Mohammed Abdulallah; Aziz, Mothanna Sh.

doi:10.1109/icasea.2018.8370955

Cited by 2 publications

(3 citation statements)

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“…In traditional communication systems, the implemented hardware of error detection and correction part is designed to deals with fixed number of information data (bits) and has no ability to be reprogramed easily to meet other requirements of different communication system. To overcome this problem a flexible hardware system can be used such as Field programmable Gated Array (FPGA) [2][3][4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

“…The transmission systems are exposing to get bits error values in either the instruction or data causing undesirable crashes or other system failures. Therefore, utilizing Hamming Code inside an embedded system is considered with high priority in modern industrial fields [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

“…-Hamming code architecture which is used as an alternative error detection code scheme in Controller Area Network technology, the implementation done on set of inputs from 8-bit to 64-bit of data frames has been explained in [15]. -A code rate of (15,11) algorithm for design Hamming code as hardware system is utilized in [16], while a code rate of (7,4) algorithm is used in with Verilog as hardware description languge [17].…”

Section: Introductionmentioning

confidence: 99%

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Design and implementation of single bit error correction linear block code system based on FPGA

Hamdoon¹,

Mohammed²,

Mohammed³

2019

TELKOMNIKA

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Linear block code (LBC) is an error detection and correction code that is widely used in communication systems. In this paper a special type of LBC called Hamming code was implemented and debugged using FPGA kit with integrated software environments ISE for simulation and tests the results of the hardware system. The implemented system has the ability to correct single bit error and detect two bits error. The data segments length was considered to give high reliability to the system and make an aggregation between the speed of processing and the hardware ability to be implemented. An adaptive length of input data has been consider, up to 248 bits of information can be handled using Spartan 3E500 with 43% as a maximum slices utilization. Input/output data buses in FPGA have been customized to meet the requirements where 34% of input/output resources have been used as maximum ratio. The overall hardware design can be considerable to give an optimum hardware size for the suitable information rate.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design and implementation of single bit error correction linear block code system based on FPGA

Hamdoon¹,

Mohammed²,

Mohammed³

2019

TELKOMNIKA

Self Cite

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Virtualizing and Scheduling FPGA Resources in Cloud Computing Datacenters

et al. 2022

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Cloud service providers consistently leverage their computing infrastructures by adding reconfigurable hardware platforms such as field-programmable gate arrays (FPGAs) to their existing infrastructures. Adding FPGAs to a cloud environment involves non-trivial challenges. The first challenge is virtualizing FPGAs as part of the cloud resources. As a standard virtualization framework is lacking, there is a need for an efficient framework for virtualizing FPGAs. Furthermore, FPGA resources are used in conjunction with central processing units (CPUs) and graphics processing units (GPUs) to accelerate the execution of tasks. Therefore, to gain the benefits of these powerful accelerating platforms, the second challenge is to optimize the allocation of tasks into the capable resources within a cloud data center. This work proposes an FPGA virtualization framework that abstracts the physical FPGAs into virtual pools of FPGA resources. The work further presents an integer linear programming (ILP) optimization model to minimize the makespan of tasks where FPGA resources are part of the cloud data center. Given the complex nature of the problem, a simulated annealing (SA) metaheuristic is developed to achieve gains in performance compared to the exact method and to scale up and handle many tasks and resources while providing nearoptimal solutions. Experimental results show that SA has reduced the makespan of a large dataset with 1000 tasks and 100 resources by up to 30% when compared to first-come-first-served (FCFS) and shortestdeadline-first (SDF) algorithms. Lastly, to quantify the performance of FPGA-enabled cloud datacenters, the work extends the CloudSim simulator (an open-source cloud simulator) to enable FPGA as a resource in its environment. The proposed virtualization framework and the SA scheduler are integrated into the environment. Simulation results show that the execution time of tasks is reduced by up to 78% when FPGA accelerators are used.

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Scheduling lecturer system based on FPGA

Cited by 2 publications

References 0 publications

Design and implementation of single bit error correction linear block code system based on FPGA

Design and implementation of single bit error correction linear block code system based on FPGA

Virtualizing and Scheduling FPGA Resources in Cloud Computing Datacenters

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