Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm

Šůcha, Přemysl; Hanzálek, Zdeník; Hermanek, Antonin; Schier, Jan

doi:10.1007/s11265-006-0004-y

Cited by 4 publications

(3 citation statements)

References 23 publications

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“…The time complexity of the presented ILP models can be further optimized by the elimination of the redundant processor constraints method [23], a polynomial algorithm reducing the size of the ILP model.…”

Section: Discussionmentioning

confidence: 99%

“…One of the simplest objectives is to minimize the iteration overlap by the objective function (4) as is assumed in this paper. Another criterion that can be directly used in this ILP model, can be used to minimize the iteration length or to minimize the number of storage units for the data transfer among the tasks [23].…”

Section: Objective Functionmentioning

confidence: 99%

“…The unit processing time of tasks cannot be assumed in some applications [23]. Therefore, we have adapted the ILP model, presented in the previous section, to the problem with an arbitrary processing time of tasks.…”

Section: Integer Linear Programming Formulation-general Processing Timementioning

confidence: 99%

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A truly two-dimensional systolic array FPGA implementation of QR decomposition

Wang¹,

Leeser

2009

ACM Trans. Embed. Comput. Syst.

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We have implemented a two-dimensional systolic array QR decomposition on a Xilinx Virtex5 FPGA using the Givens rotation algorithm. QR decomposition is a key step in many DSP applications including sonar beamforming, channel equalization, and 3G wireless communication. Compared to previous work that implements Givens rotations using a one-dimensional systolic array, our implementation uses a truly two-dimensional systolic array architecture. As a result, latency scales well for larger matrices. In addition, prior work avoids divide and square root operations in the Givens rotation algorithm by using special operations such as CORDIC or special number systems such as the logarithmic number system (LNS). In contrast, our design uses straightforward floating-point divide and square root implementations, which makes it easier to be used within a larger system. In our design, the input matrix size can be configured at compile time to many different sizes, making it easily scalable to future large FPGAs or over multiple FPGAs. The QR module is fully pipelined with a throughput of over 130MHz for the IEEE single-precision floating-point format. The peak performance for a 12 × 12 input matrix is approximately 35 GFLOPs.

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Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

Pohl

Tichý

Kadlec

2008

EURASIP J. Adv. Signal Process.

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A high performance RLS lattice filter with the estimation of an unknown order and forgetting factor of identified system was developed and implemented as a PCORE coprocessor for Xilinx EDK. The coprocessor implemented in FPGA hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programming and debugging of hardware accelerated DSP applications. The RLS lattice core extended by the order and forgetting factor estimation was implemented using the logarithmic numbers system (LNS) arithmetic. An optimal mapping of the RLS lattice onto the LNS arithmetic units found by the cyclic scheduling was used. The schedule allows us to run four independent filters in parallel on one arithmetic macro set. The coprocessor containing the RLS lattice core is highly configurable. It allows to exploit the modular structure of the RLS lattice filter and construct the pipelined serial connection of filters for even higher performance. It also allows to run independent parallel filters on the same input with different forgetting factors in order to estimate which order and exponential forgetting factor better describe the observed data. The FPGA coprocessor implementation presented in the paper is able to evaluate the RLS lattice filter of order 504 at 12 kHz input data sampling rate. For the filter of order up to 20, the probability of order and forgetting factor hypotheses can be continually estimated. It has been demonstrated that the implemented coprocessor accelerates the Microblaze solution up to 20 times. It has also been shown that the coprocessor performs up to 2.5 times faster than highly optimized solution using 50 MIPS SHARC DSP processor, while the Microblaze is capable of performing another tasks concurrently.

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Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm

Cited by 4 publications

References 23 publications

A cyclic scheduling problem with an undetermined number of parallel identical processors

A cyclic scheduling problem with an undetermined number of parallel identical processors

A truly two-dimensional systolic array FPGA implementation of QR decomposition

Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

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