Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs

Sucha, P.; Hanzálek, Zdeněk

doi:10.1109/ipdps.2006.1639404

Cited by 3 publications

(3 citation statements)

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“…The precedence relation system in (1) arises in applications such as machine scheduling (e.g., [5][6][7][8][9]), chemical process planning (e.g., [10]), smart grid (e.g., [11,12]), parallel computing (e.g., [13]) and flexible manufacture systems (e.g., [14]). In particular, in [8,9] constraints in (1) are referred to as positive and negative time-lag constraints and generalized precedence constraints, respectively.…”

Section: Application Motivationsmentioning

confidence: 99%

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Minimum equivalent precedence relation systems

Sou

2015

2015 54th IEEE Conference on Decision and Control (CDC)

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In this paper two related simplification problems for systems of linear inequalities describing precedence relation systems are considered. Given a precedence relation system, the first problem seeks a minimum subset of the precedence relations (i.e., inequalities) which has the same solution set as that of the original system. The second problem is the same as the first one except that the "subset restriction" in the first problem is removed. This paper establishes that the first problem is NP-hard. However, a sufficient condition is provided under which the first problem is solvable in polynomial-time. In addition, a decomposition of the first problem into independent tractable and intractable subproblems is derived. The second problem is shown to be solvable in polynomial-time, with a full parameterization of all solutions described. The results in this paper generalize those in [Moyles and Thompson 1969, Aho, Garey, andUllman 1972] for the minimum equivalent graph problem and transitive reduction problem, which are applicable to unweighted directed graphs.

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Section: Application Motivationsmentioning

confidence: 99%

“…Therefore, w is in fact a walk from u to v, which is denoted as w uv and stored in W in step 6. Furthermore, (13) and (15) together suggest that after the first pass of the first while-loop the degree counters (in particular those of u) are updated to…”

Section: Dmentioning

confidence: 99%

Minimum equivalent precedence relation systems

Sou

2015

2015 54th IEEE Conference on Decision and Control (CDC)

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“…As studied in [14], optimal cyclic scheduling under resource constraints is currently used to design dynamic reconfigurable circuits with FPGA.…”

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confidence: 99%

Periodic register saturation in innermost loops

Touati

Mathe

2009

Parallel Computing

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This article treats register constraints in high performance embedded VLIW computing, aiming to decouple register constraints from instruction scheduling. It extends the register saturation (RS) concept to periodic instruction schedules, i.e., software pipelining (SWP). We formally study an approach which consists in computing the exact upper-bound of the register need for all the valid SWP schedules of an innermost loop (without overestimation), independently of the functional unit constraints. We call this upper-limit the periodic register saturation (PRS) of the data dependence graph (DDG). PRS is well adapted to situations where spilling is not a favourite solution for reducing register pressure compared to ILP scheduling: spill operations request memory data with a higher energy consumption. Also, spill code introduces unpredictable cache effects and makes Worst-Case-ExecutionTime (WCET) estimation less accurate. PRS is a computer science concept that has many possible applications. First, it provides compiler designers new ways to generate better codes regarding register optimisation by avoiding useless spilling. Second, its computation can help architectural designers to decide about the most suitable number of available registers inside an embedded VLIW processor; such architectural decision can be done with full respect to instruction level parallelism extraction, independently of the chosen functional units configuration. Third, it can be used to verify prior to instruction scheduling that a code does not require spilling. In this paper, we write an appropriate mathematical formalism for the problem of PRS computation and reduction in the case of loops where data dependence graphs may be cyclic. We prove that PRS reduction is NP-hard and we provide optimal and approximate methods. We have implemented our methods, and our experimental results demonstrate the practical usefulness and efficiency of the PRS approach.

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Minimum equivalent precedence relation systems

Sou

2017

Discrete Applied Mathematics

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Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs

Abstract: This paper is motivated by existing architectures of field programmable gate arrays (FPGAsIndex Terms -Off-line scheduling, high-level synthesis, branch and bound, ILP, FPGA.

Cited by 3 publications

References 10 publications

Minimum equivalent precedence relation systems

Minimum equivalent precedence relation systems

Periodic register saturation in innermost loops

Minimum equivalent precedence relation systems

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