Scheduling with dynamic bandwidth allocation for DiffServ classes

Yang, Mei; Lu, Enyue; Zheng, S. Q.

doi:10.1109/icccn.2003.1284188

Cited by 5 publications

(8 citation statements)

References 15 publications

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“…Before we present the HDS algorithm, we first introduce the bandwidth measurement schemes at each output port, which are similar to the DDS algorithm [14]. We use L to denote the bandwidth at each output link, which is divided into two categories, reserved bandwidth and excess bandwidth.…”

Section: A Preliminariesmentioning

confidence: 99%

“…Each port scheduler has O(log N + log K log b)-gate delay, where b = max{b k | 1 ≤ k ≤ K}. The total delay of such an implementation of the HDS algorithm is O(log 2 N + log K log b)-gate delay, which is faster than the implementation of the DDS algorithm, which has O(log 2 N log b)-gate delay [14]. The construction of the central scheduler and port schedulers is also simpler than that of the DDS scheduler.…”

Section: Hardware Implementation Schemementioning

confidence: 99%

“…For EF traffic, we also consider its delay jitter performance, which is defined as the difference between the cell delays of two adjacent cells. To validate our evaluation, we compare the performance of the HDS algorithm with that of the DDS algorithm [14] and PQWRR algorithm [4].…”

Section: Performance Evaluationmentioning

confidence: 99%

“…However, the complex structure of DMS and maintenance of per-flow queues prevent its practical use. In [14], we proposed the dynamic DiffServ scheduling (DDS) algorithm, which provides minimum bandwidth guarantees for EF and AF traffic and fair bandwidth allocation for BE traffic. DDS is also a MWM-based algorithm, for which the implementation complexity is still high.…”

Section: Introductionmentioning

confidence: 99%

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Hierarchical scheduling for DiffServ classes

Yang

Wang

et al.

IEEE Global Telecommunications Conference, 2004. GLOBECOM '04.

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Abstract-Due to its simplicity and scalability, the differentiated services (DiffServ) model is expected to be widely deployed across the Internet. For each DiffServ compliant router, the scheduling algorithm is critical in implementing per hop behaviors (PHBs), according to which packets are forwarded. In this paper, we propose the hierarchical DiffServ scheduling (HDS) algorithm to support DiffServ classes on input-queued switches. The proposed HDS algorithm features in a hierarchical scheduling scheme that consists of two levels of schedulers. One level is the central scheduler which is designed to maximize the switch throughput by computing a maximal size matching between input ports and output ports. The other level is formed by input port schedulers which provide differentiated services by serving cells belonging to different classes dynamically. Using such a hierarchical scheme, the implementation complexity and the amount of information needs to be transmitted between input ports and the central scheduler are dramatically reduced compared with existing maximal weight matching based DiffServ scheduling algorithms. The tradeoff of its slightly worse delay performance is acceptable.

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Section: A Preliminariesmentioning

confidence: 99%

Section: Hardware Implementation Schemementioning

confidence: 99%

Section: Performance Evaluationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Hierarchical scheduling for DiffServ classes

Yang

Wang

et al.

IEEE Global Telecommunications Conference, 2004. GLOBECOM '04.

Self Cite

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“…However, maximum size matching algorithms are too complex for hardware implementation and can cause unfairness [2]. Most practical scheduling algorithms proposed in the literature are either maximal size matching algorithms, such as parallel iterative matching (PIM) [5], iSLIP [1], dual roundrobin matching (DRRM) [6], or maximal weight matching algorithms, such as iterative longest queue first (iLQF) and iterative oldest cell first (iOCF) [1], the longest normalized queue first (LNQF) [7], and the dynamic DiffServ scheduling (DDS) [8]. Compared with maximal size matching algorithms, maximal weight matching algorithms achieve better performance under both uniform and nonuniform traffic [1].…”

Section: Introductionmentioning

confidence: 99%

Programmable weighted arbiters for constructing switch schedulers

Yang

Zheng

Bhagyavati

et al.

2004 Workshop on High Performance Switching and Routing, 2004. HPSR.

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Abstract-As the basic building block of a scheduler based on maximal weight matching algorithms, the design of a weighted arbiter is vital to the performance of the scheduler. All existing weighted arbiter designs are based on the binary comparator tree structure and consume O(bN ) gates, where b is the number of bits needed to represent the weight. These designs are not desirable for implementing scheduling algorithms that require a large number of weighted arbiters. In light of the idea of radix sort, we propose a new weighted arbiter (WA) design and a programmable weighted arbiter (PWA) design, both with O(N ) gates. Through simulations, we show that the proposed WA design achieves significant improvement on area cost than existing WA designs. The proposed PWA design provides roundrobin fairness for requests with the same weight. Both designs can be directly used to build schedulers based on maximal weight matching algorithms. They are also useful for other applications, such as the arbitration of a shared bus and control of real-time systems.

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