Science and Cyber Security

Edgar, Thomas W.; Manz, David O.

doi:10.1016/b978-0-12-805349-2.00002-9

Cited by 61 publications

(58 citation statements)

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“…A hash function is a computational method that can map an indeterminate size of data into a fixed size of data. A cryptographic hash function uses one-way mathematical functions which are easy to calculate to generate a hash value from the input, but very difficult to reproduce the input by performing calculations on the generated hash [40]. Arora utilized the cryptographic hash function to check the instruction integrity [24].…”

Section: Bb Integrity Checkingmentioning

confidence: 99%

Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Wang

Zhao

et al. 2020

Electronics

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Nowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only closely related to the security of embedded devices, but also directly affect the performance of the processor. This paper presents a security monitoring and fault recovery architecture for run-time program execution, which takes regular backup copies of the two-stage checkpoint. In this framework, the integrity check technology based on the basic block (BB) is utilized to monitor the program execution in real-time, while the rollback operation is taken once the integrity check is failed. In addition, a Monitoring Cache (M-Cache) is built to buffer the reference data for integrity checking. Moreover, a recovery strategy mainly for three tampered positions (registers in processor, instructions in Cache, and codes in memory) is provided to ensure the smooth running of the embedded system. Finally, the open RISC processor is adopted to implement and verify the presented security architecture, which has been proved to be effective for program detection in the execution of tamper attack and quick recovery of the running environment as well as code.

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Section: Bb Integrity Checkingmentioning

confidence: 99%

Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Wang

Zhao

et al. 2020

Electronics

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“…Firewalls, system event logs, antivirus software, packet captures, net flow collectors, and intrusion detection systems are examples of common cyberspace sensors. 6 Level-two technologies generate information from the data to determine a current situation. Generally, level-two technologies require the bringing together of data and performing some level of analytics.…”

Section: Security Management and Governancementioning

confidence: 99%

“…Cyber-threat intelligence provides information on active threat actor methods, techniques, and targets providing some level of predictive information to enable taking pre-emptive security measures. 6 Artificial intelligence for cybersecurity develops with high speed and offers new possibilities for better SA.…”

Section: Security Management and Governancementioning

confidence: 99%

Resilience Management Framework for Critical Information Infrastructure: Designing the Level of Trust that Encourages the Exchange of Health Data

Rajamäki¹

2020

ISIJ

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This article presents the conceptual resilience governance framework and design aspects for resilient cyber-physical eHealth systems. Our safety and security thinking has been based on the supposition that inside defensive walls we are safe. The focus of our actions has been the control of our own systems, the improvement of the protection and staying inside the protection. However, nobody is able to control complex large integrated cyber-physical systems while, on the other hand, coordination and cooperation are needed. In eHealth, this means that the focus is moved from the control and securing of health information towards utilising of eHealth to promote health. On the other hand, we have an urgent need to complement the existing knowledgebase of safety and risk management by developing frameworks and models enabling network-wide resilience management that strives for maintaining and improving critical functionalities.

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“…In the subsequent hardware postprocessing, SRAM is repeatedly powered on to get true random bitstreams continuously. During each power-on cycle, every n bits of power-on values are integrated into one block, which is conditioned into a 256-bit true random string with full entropy (i.e., the amount of entropy in the string is equal to its length [20,29]) by means of SHA-256 hash function. In order for the output string of SHA-256 to have full entropy (256 bits), the amount of entropy at the input of the hash function should be at least 256 bits [19,30].…”

Section: Proposed Sram-based Trng Schemementioning

confidence: 99%

Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure

Zhang

Jiang

Dai

et al. 2020

Sensors

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Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers, benefiting from noisy SRAM cells whose start-up values flip between different power-on cycles. Embarking from this phenomenon, a novel performance (i.e., randomness and throughput) improvement method of SRAM-based TRNG is proposed, and its implementation can be divided into two phases: irradiation exposure and hardware postprocessing. As the randomness of original SRAM power-on values is fairly low, ionization irradiation is utilized to enhance its randomness, and the min-entropy can increase from about 0.03 to above 0.7 in the total ionizing irradiation (TID) experiments. Additionally, while the data remanence effect hampers obtaining random bitstreams with high speed, the ionization irradiation can also weaken this impact and improve the throughput of TRNG. In the hardware postprocessing stage, Secure Hash Algorithm 256 (SHA-256) is implemented on a Field Programmable Gate Array (FPGA) with clock frequency of 200 MHz. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps utilizing SRAM chip with 1 Mbit memory capacity. Furthermore, according to different application scenarios, the throughput can be widely scalable by adjusting clock frequency and SRAM memory capacity, which makes the novel TRNG design applicable for various Internet of Things (IOT) devices.

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Science and Cyber Security

Cited by 61 publications

References 0 publications

Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Resilience Management Framework for Critical Information Infrastructure: Designing the Level of Trust that Encourages the Exchange of Health Data

Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure

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