<scp>A</scp> low‐phase‐noise and low‐power CMOS colpitts VCO using G<sub>m</sub> boosting and capacitance switching techniques

Pakasiri, Chatrpol; You, Jia‐Hao; Wang, Sen

doi:10.1002/mop.32550

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…The citations cover a wide range of topics related to oscillator design, including low-phase noise design, low-power operation, frequency dividers, and various techniques for improving VCO performance. There are some recent works but with different CMOS process, techniques, and carrier frequency are cited in [27][28][29][30][31].…”

Section: Comparison With Previous Workmentioning

confidence: 99%

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Siddiqui,

Maheshwari,

Raza

et al. 2023

JLPEA

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This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

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Section: Comparison With Previous Workmentioning

confidence: 99%

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Siddiqui,

Maheshwari,

Raza

et al. 2023

JLPEA

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show abstract

“…Using filters or additional inductors is another solution to decreasing phase noise, but such technique is infeasible because of the occupied chip area and the difficulties encountered in the design and F I G U R E 1 Schematic of conventional LC oscillator manufacture of inductors for integrated circuits. A Gm-boosting VCO using capacitance switching techniques was presented in Chatrpol et al 25 Using PMOS cross-coupled pair similar to Colpitts with two pairs of switched capacitor array increases output power and reduces phase noise simultaneously.…”

Section: Studies On Lc Oscillatorsmentioning

confidence: 99%

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

Kebria

Ghonoodi

2020

Circuit Theory & Apps

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SummaryThis study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to −123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to −193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.

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Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor

Kumar

2023

J. Inst. Eng. India Ser. B

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A low‐phase‐noise and low‐power CMOS colpitts VCO using G_m boosting and capacitance switching techniques

Cited by 3 publications

References 9 publications

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor

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A low‐phase‐noise and low‐power CMOS colpitts VCO using Gm boosting and capacitance switching techniques

Cited by 3 publications

References 9 publications

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor

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A low‐phase‐noise and low‐power CMOS colpitts VCO using G_m boosting and capacitance switching techniques