Three‐stage CMOSamplifier: Frequency compensated using fully differential block

Abstract

The advancement of CMOS technology limits designers' options for multi‐stage configurations as a promising alternative to cascade structures. The main issue of designing multi‐stage amplifiers is frequency compensation since cascade structures are volatile. An efficient three‐stage amplifier, which is frequency compensated using a fully differential block, is proposed in this work. The differential block enhances the Miller effect to reduce the size of compensation capacitors, and this leads to less die occupation. The compensation network shares the differential block between two Miller loops while two Miller capacitors at the outputs of the differential block cause pole‐zero cancelation to increase operating frequency range. The proposed structure is modeled by a linear transfer function and simulated via HSPICE software using 0.180.25emμm0.25em CMOS library. Simulation results indicate excellent performance and acceptable robustness against parameter mismatches and probable fabrication errors. According to the simulations, the proposed amplifier has a DC gain of 1050.25emdB, a gain‐bandwidth product of 4.80.25emMHz, a phase margin of 72°, and a power dissipation of 3600.25emμW. The high performance of the proposed three‐stage amplifier with an enhanced figure of merit makes it a perfect alternative to the amplifiers based on the conventional reverse nested Miller compensation.

Multi‐Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

“…In contrast to cascode structures, the major problem of designing a multistage amplifier is stability issues. Usually, adding a frequency compensation network to the main amplifier stabilizes the signal amplification under specific conditions [9][10][11][12][13][14][15][16][17].…”