Seamless high off-chip connectivity [IC packaging]

Schaper, L.W.; Dibbs, M.; Garrou, Philip E.; Chau, C. C.; So, Y.; Frye, D.; Wagner, Jan; Ousley, J.; Baugher, G.; Picard, Richard R.; Connor, G.; Winn, D.; Deane, P.; Eden, R.C.; Sands, R.

doi:10.1109/ipdi.1998.663617

Cited by 8 publications

(3 citation statements)

References 5 publications

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“…Although the results from the model indicate that most current high I/O density packages may reasonably be used in conjunction with commodity substrates, the use of such packages alongside much lower I/O density packages may not be the most efficient method of designing a complete product or system. Schaper et al, 1998 methodology for distributing the interconnectivity of a system throughout the various system levels. The primary question addressed by the methodology is at what system level should various interconnections be made to optimise the design electrically and physically.…”

Section: Discussionmentioning

confidence: 99%

The constraints of vias and layers and their impact on PCB design strategy

Palmer

Williams

1999

Circuit World

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This paper explores the use of models of substrate behaviour to examine the wireability constraints on PCBs due to signal layers and buried and through vias. The importance of product scale as a factor affecting technology choice is examined in detail, and the factors that decide the need for multi‐layer construction and buried and through vias are discussed. Large PCB layouts are constrained by lack of space for traces ‐ trace bound; a limitation that can be removed by using multi‐layers and through hole vias. Small PCB layouts are constrained by lack of space for vias ‐ via bound; buried vias and landless vias are particularly useful for maximising wiring density under these conditions. A further observation is that the use of multiple layers offers diminishing returns as each further layer is added. For small high wiring density PCBs approximately four layers supporting blind vias can give excellent support for the use of high I/O (Input/Output) density packages.

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Section: Discussionmentioning

confidence: 99%

The constraints of vias and layers and their impact on PCB design strategy

Palmer

Williams

1999

Circuit World

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“…Depending on the application, an efficient memory management scheme can lead to better memory bandwidth utilization and give almost SRAM-like performance. SHOCC is a combined packaging, interconnect, and IC design technology aimed at providing system-level integration by using very high density solder bump and thin-film technologies [1], [2]. The purpose of this paper is to show how the use of such a technology can result in a radical performance improvement in a specific application.…”

Section: Introductionmentioning

confidence: 99%

Optimal chip-package codesign for high-performance DSP

Mehrotra

Rao

Conte

et al. 2005

IEEE Trans. Adv. Packag.

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In high-performance DSP systems, the memory bandwidth can be improved using high-density interconnect technology and appropriate memory mapping. High-density MCM and flip-chip solder bump technology is used to achieve a system with an I/O bandwidth of 100 Gb/s/cm 2 die. The use of DRAMs in these systems usually make the performance of these systems poor, and some algorithms make it difficult to fully utilize the available memory bandwidth. This paper presents the design of an fast Fourier transform (FFT) engine that gives SRAM-like performance in a DRAM-based system. It uses almost 100% of the available burst-mode memory bandwidth. This FFT engine can compute a million-point FFT in 1.31 ms at a sustained computation rate of 8.6410 10 floating-point operations per second (FLOPS). This is at least an order of magnitude better than conventional systems. Index Terms-Chip-package codesign, fast Fourier transform (FFT), seamless high off-chip connectivity (SHOCC).

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“…This idea has been proposed by several groups [10]- [11], with the thin-film wiring provided in one of several forms (chip-scale packaging, multi-chip module (MCM), etc.). The authors in [10] use the term DiePack to describe such implementations, a couple of which are illustrated in Fig.…”

Section: Potential Solutions To the Interconnect Bottleneckmentioning

confidence: 99%

The interconnect bottleneck in multi-GHz processors; new opportunities for hybrid electrical/optical solutions

Cangellaris

Proceedings. Fifth International Conference on Massively Parallel Processing (Cat. No.98EX182)

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The semiconductor industry appears to be confident that, even without any major breakthroughs in photolithography, it will be able to achieve device feature sizes in the order of 100 nm by the year 2006. This reduction in feature size implies significantly higher device switching speeds and faster circuits. More specifically, microprocessors with 3 GHz on-chip clock frequency are within reach by the year 2006. The only obstacle to such an impressive level of performance, both across the chip and beyond the chip at the system level, is the availability of an interconnection network of unprecedented complexity and capable of supporting multi-GHz-bandwidth, distortion-and interference-free propagation both on-chip and off-chip. This interconnect bottleneck to multi-GHz processor realization is examined in this paper. The emphasis is on the evaluation of the most promising and cost-effective electrical ways of overcoming this bottleneck. It is argued that some of these potential solutions involve technologies that are compatible with on-going developments in optical interconnects. Thus, an opportunity is identified for bringing together electrical and optical interconnect technologies at a level in the integration hierarchy where traditionally optics is considered to be at a disadvantage, namely, at the chip and chip-to-package interconnect level.

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Seamless high off-chip connectivity [IC packaging]

Cited by 8 publications

References 5 publications

The constraints of vias and layers and their impact on PCB design strategy

The constraints of vias and layers and their impact on PCB design strategy

Optimal chip-package codesign for high-performance DSP

The interconnect bottleneck in multi-GHz processors; new opportunities for hybrid electrical/optical solutions

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