SEARS: A Statistical Error and Redundancy Analysis Simulator

Atishay,; Gupta, Ankit; Sonawat, Rashmi; Thacker, Helik Kanti; Prasanth, B.

doi:10.1109/vlsi-soc.2019.8920344

Cited by 6 publications

(2 citation statements)

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“…Atishay et al [57] presented a statistical error and redundancy analysis simulator which generates faults similar to the manufacturing environment for DRAM. Most other fault simulators, including [55], generate defects randomly or use Binomal or Polya-Eggenberger distribution model, which does not represent defects on wafers.…”

Section: Simulators For Measuring Reliability and Repair Efficiencymentioning

confidence: 99%

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Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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Section: Simulators For Measuring Reliability and Repair Efficiencymentioning

confidence: 99%

“…Based on the results, changes could be made to improve yield further. Simulators like those presented in [57] and [58] could be effectively used for this purpose. Similarly, methodologies presented to estimate the memory lifetime could be used as an addition.…”

mentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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A Statistical Wafer Scale Error and Redundancy Analysis Simulator

Atishay¹,

Gupta²,

Sonawat³

et al. 2020

IFIP Advances in Information and Communication Technology

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Manufacturing a DRAM chip involves multiple steps. External impurities, faulty deposition, or manufacturing errors in any of these steps could generate chips with faulty memory cells, rendering the chip unusable. To overcome these faulty memory cells, redundancies are included in the memory, allowing mapping of faulty memory cells to these redundant cells. The process of mapping faulty cells to redundant cells is called Redundancy Analysis (RA). Different RA algorithms have been developed and are often tested on randomly generated defect to test their efficiency and execution time. But we observed that, the defect pattern of a chip is not completely random, it follows a distribution pattern and the algorithms should be tested on chips with similar error distribution patterns. So, in this paper, we propose a Statistical Wafer Scale Error and Redundancy Analysis Simulator to generate defects on the chips similar to defects on the manufacturing line. The simulated errors on the chips are based on statistical models derived from real data. After generating defects on the chip, execution, comparison and benchmarking of algorithms based on yield and execution time is done. The simulator gives insights on algorithm behavior with different kinds of memory architectures and defect patterns. This allows designers of memory architecture and RA algorithm to simulate, predict and improve the wafer yield for different RA algorithm designs and memory architectures before manufacturing a new memory device.

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