SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection

Abstract

Shrinking process technology and rising memory densities have made memories increasingly vulnerable to errors. Accordingly, DRAM vendors have introduced On-die Error Correction Code (O-ECC) to protect data against the growing number of errors. Current O-ECC provides weak Single Error Correction (SEC), but future memories will require stronger protection as error rates rise. This paper proposes a novel ECC, called Single Error Correction-Byte-Aligned Double Adjacent Error Correction (SEC-BADAEC) and its construction algorithm to improve memory reliability. SEC-BADAEC requires the same redundancy as SEC O-ECC, but it can also correct some frequent 2-bit error patterns. Our evaluation shows SEC-BADAEC can improve memory reliability by 23.5% and system-level reliability by 29.8% with negligible overheads.

On-Chip Bus Protection against Soft Errors

“…Then, if an entire DRAM chip experiences a hard fail and stops functioning, the data in that DRAM can be recovered using the other DRAM chips and the checksum [21]. The studies [27,28] compare different EDAC schemes for memories regarding hardware overhead, time overhead, and error correction and detection capabilities. Similarly, the study [29] compares existing approaches for L1 data cache error protection concerning performance, L2 cache bandwidth, power consumption, and area.…”

Review of Memory RAS for Data Centers

“…Generally, multiple errors are located in close proximity to each other. To address these, there is a method called SEC-DAEC (Single Error Correction-Double Adjacent Error Correction) that can correct up to two adjacent errors [64][65][66]. As one of the SEC-DAEC skills, the interleavedparity (IP) method can be utilized.…”