Secondary radix recodings for higher radix multipliers

High-Speed and Low-Power PID Structures for Embedded Applications

“…Most of the proposals aimed to reduce the number of partial products either by employing digital optimization techniques [7][8] [9] or by using larger slices (higher radices) [10]. However, experience showed [11] that beyond 4-bit slices (radix 8), the complexity to generate hard partial products can not be managed in a realistic way. In [11], three metrics are provided for comparing the tradoffs when employing higher radix Booth recodings: partial product compression factor (gain), the number of hard multiples that must be precomputed (computation complexity), and partial product generation fanin (routing complexity).…”

A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier

“…The current trend [8][9] relies upon advanced arithmetic to determine minimal numeric bases that are representatives of the digits resulting from larger multibit recoding. The objective is to eliminate information redundancy inside r+1 bit-length slices for a more compact PPG.…”

“…In [8], Seidel et al have introduced a secondary recoding of digits issued from an initial multibit recoding for 5≤r≤16. The recoding scheme is based on balanced complete residue system.…”

“…Several higher radix (ß=2 3 , 2 32 ) two's complement 64x64 bit serial/parallel multipliers based on combined recoding schemes are implemented on Virtex-6 FPGA and characterized in terms of speed, power, and area occupation for r values ranging from 2 to 64. Compared to a new signed version of Dimitrov et al algorithm [9] and Seidel et al algorithm [8], outstanding results are obtained with the new multibit recoding scheme for r=8 formed by the combination of Seidel algorithm (r=5), MacSorley algorithm (r=2) [2] and Booth algorithm (r=1) [10]. The respective savings are as follows: 21%, 53%, 105% and 8%, 52%, 63% are obtained in terms of multiply-time, energy consumption per multiplyoperation, and total gate count, respectively.…”

“…It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (n/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (ß≥8) multiplication. Based on a mathematical proof that any higher radix ß=2 r can be recursively derived from a combination of two or a number of lower radices, a series of generalized radix ß=2 r multipliers are generated by means of primary radices: 2 1 , 2 2 , 2 5 , and 2 8 . A variety of higher-radix (2 3 -2 32 ) two's complement 64x64 bit serial/parallel multipliers are implemented on Virtex-6 FPGA and characterized in terms of multiply-time, energy consumption per multiply-operation, and area occupation for r value varying from 2 to 64.…”