Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance

Sonoda, Hiroki; Monta, Kazuki; Okidono, Takaaki; Araga, Yuuki; Watanabe, Naoya; Shimamoto, H.; Kikuchi, Katsuya; Miura, Noriyuki; Miki, Takuji; Nagata, Makoto

doi:10.1109/iedm13553.2020.9372073

Cited by 3 publications

(1 citation statement)

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“…Figure 10 depicts a 3D secure packaging structure. 34,35) All IO pads of each chip are vertically connected to the BBM of the upper tier formed on the backside of the chip via through-silicon vias and microbumps. The BBM also forms a power and ground wiring network; thus, a MOS capacitance is formed between the BBM and the Si substrate via SiO 2 .…”

Section: Detection Of Si-backside Attacksmentioning

confidence: 99%

Countermeasures against physical security attacks on ICs utilizing on-chip wideband ADCs

Miki

Nagata

2022

Jpn. J. Appl. Phys.

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Cryptographic ICs on edge devices for internet-of-things (IoT) applications are exposed to an adversary and threatened by malicious side channel analysis. On-chip analog monitoring by sensor circuits embedded inside the chips is one of the possible countermeasures against such attacks. An on-chip monitor circuit consisting of a successive approximation register (SAR) analog-to-digital converter (ADC) and an input buffer acquires a wideband signal, which enables to detects an irregular noise due to an active fault injection and a passive side channel leakage analysis. In this paper, several countermeasures against security attacks utilizing wideband on-chip monitors are reviewed. Each technique is implemented on a prototype chip, and the measurement results prove they can effectively detect and diagnose the security attacks.

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Section: Detection Of Si-backside Attacksmentioning

confidence: 99%