Secure and Dependable NoC-Connected Systems on an FPGA Chip

Wehbe, Taimour; Wang, Xiaofang

doi:10.1109/tr.2016.2606883

Cited by 21 publications

(6 citation statements)

References 30 publications

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“…On the other hand, the malicious attacks for electronic transmission of ΔP values within E-net are similar to those modeled in the previous relevant works in the NoCs [18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36]. After all, as one sort of control data, the temperature information is also prone to be under data leakage and manipulation as mentioned [41,42], causing negative impacts on the performance and reliability of ONoCs.…”

Section: Figure 6: An Mr-based Thermal Sensor With Hts For Onocssupporting

confidence: 69%

“…7) Mixed scheme. [33] proposed an integrated runtime solution for both security and fault tolerance of SoCs based on the field-programmable gate array (FPGA) through digital signatures, live monitoring, partial reconfiguration, and adaptive routing supported by an ENoC called X-Network that can reduce the ratio of required routers versus PEs to facilitate security designs and fault tolerance. In [34], authors offered Fort-NoCs, a series of techniques including data scrambling, packet certification, and node obfuscation, to disable covert backdoor activation and reduce the chance of encountering the side-channel attacks by "clouding" the information obtained by the attackers for defense against the compromised ENoC in MPSoC.…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…Prior related works [18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36] seldom focused on the security of control information, but that of data packets of networks. According to the thermal sensing flow in ONoCs mentioned above, some serious kinds of HT attacks can be triggered by the embedded counterfeit circuits.…”

Section: Attack Modelmentioning

confidence: 99%

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Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs

Zhou

Guo

et al. 2021

J. Emerg. Technol. Comput. Syst.

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As an emerging role in new-generation on-chip communication, optical networks-on-chip (ONoCs) provide ultra-high bandwidth, low latency, and low power dissipation for data transfers. However, the thermo-optic effects of the photonic devices have a great impact on the operating performance and reliability of ONoCs, where the thermal-aware control with accurate measurements, e.g., thermal sensing, is typically applied to alleviate it. Besides, the temperature-sensitive ONoCs are prone to be attacked by the hardware Trojans (HTs) covertly embedded in the counterfeit integrated circuits (ICs) from the malicious third-party vendors, leading to performance degradation, denial-of-service (DoS), or even permanent damages. In this article, we focus on the tampering and snooping attacks during the thermal sensing via micro-ring resonator (MR) in ONoCs. Based on the provided workflow and attack model, a new structure of the anti-HT module is proposed to verify and protect the obtained data from the thermal sensor for attacks in its optical sampling and electronic transmission processes. In addition, we present the detection scheme based on the spiking neural networks (SNNs) to implement an accurate classification of the network security statuses for further high-level control. Evaluation results indicate that, with less than 1% extra area of a tile, our approach can significantly enhance the hardware security of thermal sensing for ONoC with trivial costs of up to 8.73%, 5.32%, and 6.14% in average latency, execution time, and energy consumption, respectively.

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Section: Figure 6: An Mr-based Thermal Sensor With Hts For Onocssupporting

confidence: 69%

Section: Related Work and Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs

Zhou

Guo

et al. 2021

J. Emerg. Technol. Comput. Syst.

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“…The major malicious behaviors along this line include denial of service (DoS) [107], linker behavior [26], [27], and router behavior [108], which are launched by HTs implanted in links or routers. Attackers may exploit covert communication [73], [109], bus idle states [110], and peripheral interfaces [28] to disclose confidential information, tamper with communication data, interfere with normal operations, and perform DoS attacks.…”

Section: -Implantation Preventionmentioning

confidence: 99%

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

et al. 2020

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The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.

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“…However, these architectures fail to meet the scalability issues. The NoC provides scalability solutions by replacing current bus-based architecture with an interconnected network for SoC's [1]. To provide high performance and low power requirements in SoC's, the NoC provides the communication platform among the IP cores.…”

Section: Introductionmentioning

confidence: 99%

Design of an Efficient Fault and Congestion Free NoC Design using Adaptive Routing on FPGA

S.P*¹,

B.S²

2019

IJRTE

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Manufacturing fault-free System on Chips (SoCs) with performance scaling is a challenging task. The Network on Chip (NoC) architecture offers scalability and reliability to the SoC designs. In this paper, the fault detection and correction mechanism for a congestion-free Router architecture along with Mesh-NoC for different sizes are discussed. The proposed hardware architecture of NoC-Router includes Input registers (which store five -port inputs with Fault injection), Error Correction Code (that encodes the input data) followed by packet formation with Arbitration mechanism (that grants the permission to priority based encoder). The prior packet data is input to the adaptive-XY routing and it operates with the various congestion issues on choosing the shortest route. The detection and correction of the faulty bits from the network are monitored by ECC decoder. This NoC router can tolerate transient fault; provides low-latency and high throughput performance for all MPSoC applications. The Normal –XY Routing algorithm is incorporated in same router for comparison purpose. The synthesis results includes chip area, and maximum operating frequency over Artix-7 FPGA technology. Outcomes are tabulated and they show a marked improvement over previous cases. The performance evaluation is considered in terms of average latency and maximum throughput at different input traffic. It’s analyzed for novelty features as well.

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Secure and Dependable NoC-Connected Systems on an FPGA Chip

Cited by 21 publications

References 30 publications

Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs

Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

Design of an Efficient Fault and Congestion Free NoC Design using Adaptive Routing on FPGA

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