SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration

Devic, Florian; Torres, Lionel; Crenne, Jérémie; Badrignans, Benoit; Benoit, Pascal

doi:10.1109/fpl.2012.6339241

Cited by 14 publications

(8 citation statements)

References 7 publications

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“…In [7][8][9][10] the FPGA designs including a processor to manage Ethernet frames, which greatly increases the overhead of FPGA resources are presented. In [7,9] use as encryption algorithm Output Feedback (OFB) and [8] uses Cipher Feedback (CBC). In [28], algorithms implemented in the FPGA to manage Ethernet frames are used, but no encryption method is used.…”

Section: Comparison With Existing Schemesmentioning

confidence: 99%

“…In this case, an alternative is to include in the design a module that allows remote communication management. Among others, in [7][8][9][10] to manage Ethernet configuration frames, they propose the use of a microprocessor-based module. This solution has the disadvantage that it is costly in terms of physical resources and power required; furthermore, the complexity of the design increases and the configuration speed decreases.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid

Urbina

Moreira

Rodríguez³

et al. 2018

Energies

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Nowadays, the incorporation and constant evolution of communication networks in the electricity sector have given rise to the so-called Smart Grid, which is why it is necessary to have devices that are capable of managing new communication protocols, guaranteeing the strict requirements of processing required by the electricity sector. In this context, intelligent electronic devices (IEDs) with network architectures are currently available to meet the communication, real-time processing and interoperability requirements of the Smart Grid. The new generation IEDs include an Field Programmable Gate Array (FPGA), to support specialized networking switching architectures for the electric sector, as the IEEE 1588-aware High-availability Seamless Redundancy/Parallel Redundancy Protocol (HSR/PRP). Another advantage to using an FPGA is the ability to update or reconfigure the design to support new requirements that are being raised to the standards (IEC 61850). The update of the architecture implemented in the FPGA can be done remotely, but it is necessary to establish a cyber security mechanism since the communication link generates vulnerability in the case the attacker gains physical access to the network. The research presented in this paper proposes a secure protocol and Intellectual Property (IP) core for configuring and monitoring the networking IPs implemented in a Field Programmable Gate Array (FPGA). The FPGA based implementation proposed overcomes this issue using a light Layer-2 protocol fully implemented on hardware and protected by strong cryptographic algorithms (AES-GCM), defined in the IEC 61850-90-5 standard. The proposed secure protocol and IP core are applicable in any field where remote configuration over Ethernet is required for IP cores in FPGAs. In this paper, the proposal is validated in communications hardware for Smart Grids.

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Section: Comparison With Existing Schemesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid

Urbina

Moreira

Rodríguez³

et al. 2018

Energies

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“…If some bytes are missing then the above-described postprocessing step [based on Eqs. (8) and (9) and the results from Appendix] must be performed to recover them. If M E B 1,2 is used and the index 14 of K Nr−1 was not recovered then Algorithm 2 must be executed with the tampering function π(g, d, y), but using the above-proposed T-Boxes' content relationship to avoid the masking of this index.…”

Section: Effects Of the Multiplication Elimination Block On The Attackmentioning

confidence: 99%

“…A similar attack can be carried out to the protocol proposed in [8] to defend against bitstream replay attacks. The authors propose the protocol in figure 4 of [8] for securing the partial reconfiguration procedure of a FPGA device.…”

Section: Application Examplesmentioning

confidence: 99%

AES T-Box tampering attack

2015

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The use of embedded block memories (BRAMs) in Xilinx FPGA devices makes it possible to store the T-Boxes that are employed to implement the AES block cipher's SubBytes and MixColumns operations. Several studies into BRAM resistance to side-channel attacks have been reported in the literature, whereas this paper presents a novel attack based on tampering the BRAMs storing the T-Boxes. This approach allows recovering the key using a ciphertextonly attack for all AES key sizes. The complexity of the attack makes it completely feasible. The attack was mounted against previously reported FPGA-based AES implementations, taking into account the different design criteria used in each case and focusing mainly on the implementation of the final round of the AES algorithm, which plays a crucial role in the analysis. Three different final round implementations extracted from well-known existing architectures are analyzed in this work. The paper also discusses some countermeasures with regard to security, performance and FPGA resource utilization. The attack is presented against FPGAbased implementations but it can be extended to software architectures as well.

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“…Devic et al present in [4] and [5] a secure protocol and an implementation which offer remote bitstream updates. They foresee countermeasures against replay attacks and bitstream spoofing and provide a solution without the need for external memory.…”

Section: A Remote Reconfiguration Of An Fpgamentioning

confidence: 99%

A single-chip solution for the secure remote configuration of FPGAs using bitstream compression

Vliegen

Mentcns

Verbauwhede

2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Abstract-This paper presents a system that allows the secure remote configuration of an FPGA, which is assumed to be the only device in the secure zone. This means that no security critical information passes over the borders of the FPGA chip, reducing the opportunities for an attacker to break the system. In particular, bitstream compression in combination with partial reconfiguration is used to avoid the use of an external memory for the storage of the bitstream. Additionally there is no need for an external processor for the transfer of the bitstream. Nevertheless, our solution contains a mechanism that verifies the integrity of the complete bitstream before starting the configuration. This prevents attempts to load unqualified bitstreams and reduces the downtime. The integrity check, the decryption, the authentication of the origin and the freshness check of the bitstream are performed inside the FPGA while its current configuration is still active. The contribution of this work is that it presents the first complete working system for the secure remote configuration of FPGAs, consisting of a single FPGA chip and an initiating server, given that the integrity of the complete bitstream is verified before configuration. This paper gives details on the overall system and the FPGA architecture, which have been implemented and tested.

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SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration

Cited by 14 publications

References 7 publications

Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid

Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid

AES T-Box tampering attack

A single-chip solution for the secure remote configuration of FPGAs using bitstream compression

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