Secure Force: A low-complexity cryptographic algorithm for Wireless Sensor Network (WSN)

Ebrahim, Mansoor; Chong, Chai Wai

doi:10.1109/iccsce.2013.6720027

Cited by 37 publications

(14 citation statements)

References 7 publications

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“…Overall, the process of SF algorithm consists of 4 major blocks. The detail description of search block of the proposed algorithm can be found in [1].…”

Section: The Secure Force Algorithmmentioning

confidence: 99%

“…The top level entity named SF combines all three modules together to form a complete single-unit to implement it on Altera DE2 board. First, a 64-bit key passes through the key generator which generates K1, K2, K3, K4, and K5 that are also 64-bit keys for all five rounds as mentioned in [1]. These five keys (K1 to K5) will be used by the encryption block which takes the plain text from the IOs and converts it into a cipher text of 64-bits by applying the encryption process, which consists of five rounds.…”

Section: Proposed Secure Force Architecture For Fpga Implementationmentioning

confidence: 99%

“…The key expansion performs logical operations (XOR, XNOR), left shifting (LS), matrix multiplication using fix matrix (FM), permutation using P-table and transposition using T-table. The detailed block diagram of key expansion and round scheduling is available in [1].…”

Section: Key Expansion Blockmentioning

confidence: 99%

“…Fixed Matrix Multiplication: As proposed in [1], the key expansion block requires the multiplication of four fixed matrices. The fixed matrix multiplication produces bounded results.…”

Section: Functional Logic Blockmentioning

confidence: 99%

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FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

Khan¹,

Ibrahim²,

Ebrahim³

et al. 2015

IJCNIS

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Abstract-Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers, a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently proposed Secure Force (SF) shows good results in terms of resource utilization compared to older ciphers. SF appears as a promising choice for power and resource constrained secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a full loopunroll implementation of SF-64 on FPGA. This work provides hardware characteristics of SF along with implementation results that are optimal in terms of throughput, latency, power utilization and area efficiency.

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“…Overall, the process of SF algorithm consists of 4 major blocks. The detail description of search block of the proposed algorithm can be found in [1].…”

Section: The Secure Force Algorithmmentioning

confidence: 99%

Section: Proposed Secure Force Architecture For Fpga Implementationmentioning

confidence: 99%

Section: Key Expansion Blockmentioning

confidence: 99%

“…Fixed Matrix Multiplication: As proposed in [1], the key expansion block requires the multiplication of four fixed matrices. The fixed matrix multiplication produces bounded results.…”

Section: Functional Logic Blockmentioning

confidence: 99%

See 2 more Smart Citations

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

Khan¹,

Ibrahim²,

Ebrahim³

et al. 2015

IJCNIS

Self Cite

View full text Add to dashboard Cite

show abstract

“…Various cryptographic algorithms can be used to encrypt an image [10] but, for WMSN we require an algorithm with less computational complexity and high reliability. For this purpose, we have chosen Secured Force encryption technique [11]. This technique performs well on the grounds of code complexity and complex key expansion where, it takes only five rounds for the encryption and performs the expansion process at data sink which, in turn, saves a lot of energy at the sensor nodes.…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Approach for Simultaneous Compression and Encryption of an Image in Wireless Media Sensor Networks

Karthikeyan

Srividhya

Gupta

et al. 2016

Advanced Computing and Communication Technologies

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In this paper, the advantages of discrete cosine transform and discrete wavelet transform have been harnessed by considering them together for compression, followed by an energy efficient Secured Force encryption technique. This was done in order to simultaneously compress and encrypt the image that has to be transmitted through Wireless Media Sensor Network (WMSN). The proposed technique provides better and faster compression as compared to the existing techniques. Results show that, there is an average increase of 4 % in compression with respect to DCT based compression and DWT based compression. Also, in the proposed approach, Chroma cr. matrix is used for quantization, which has reduced the total processing time by a huge amount as compared to the other quantization matrices.

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A Robust Lightweight Algorithm for Securing Data in Internet of Things Networks

Al‐Ahdal

AL-Rummana

Deshmukh

2021

Sustainable Communication Networks and Application

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Secure Force: A low-complexity cryptographic algorithm for Wireless Sensor Network (WSN)

Cited by 37 publications

References 7 publications

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

A Hybrid Approach for Simultaneous Compression and Encryption of an Image in Wireless Media Sensor Networks

A Robust Lightweight Algorithm for Securing Data in Internet of Things Networks

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